Microprocessor The operations executed by two or more control units are referred as Macro-operations Multi-operations Micro-operations Bi control-operations Macro-operations Multi-operations Micro-operations Bi control-operations ANSWER DOWNLOAD EXAMIANS APP
Microprocessor If the number of address bits in a memory is reduced by 2 and the addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory) Halves Doubles Increases by 2^(address bits)/addressability Remains unchanged Halves Doubles Increases by 2^(address bits)/addressability Remains unchanged ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. None of these Both ‘b’ and ‘c’ Bus Interface Unit (BIU) Execution Unit (EU) None of these Both ‘b’ and ‘c’ Bus Interface Unit (BIU) Execution Unit (EU) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The relation among IC (Instruction Cycle), FC (Fetch cycle) and EC (Execute Cycle) is IC = FC + 2EC EC = IC + FC IC = FC - EC IC = FC + EC IC = FC + 2EC EC = IC + FC IC = FC - EC IC = FC + EC ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The output data lines of microprocessor and memories are usually tristated because The data line can be multiplexed for both input and output More than one device can transmit over the data bus at the same time It increases the speed of data transfer over the data bus More than one device can transmit information over the data bus by enabling only one device at a time The data line can be multiplexed for both input and output More than one device can transmit over the data bus at the same time It increases the speed of data transfer over the data bus More than one device can transmit information over the data bus by enabling only one device at a time ANSWER DOWNLOAD EXAMIANS APP
Microprocessor If m is a power of 2, the number of select lines required for an m-input mux is: 2*m 2^m m log2 (m) 2*m 2^m m log2 (m) ANSWER DOWNLOAD EXAMIANS APP
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