Microprocessor During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? T1 OP code fetch T4 OP code fetch T2 OP code fetch T3 OP code fetch T1 OP code fetch T4 OP code fetch T2 OP code fetch T3 OP code fetch ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The execution of RST n instruction causes the stack pointer to None of these decrement by two increment by two remain unaffected None of these decrement by two increment by two remain unaffected ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following interrupt is both level and edge sensitive? INTR RST 5.5 TRAP RST 7.5 INTR RST 5.5 TRAP RST 7.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor At the beginning of a fetch cycle, the contents of the program counter are incremented by one. transferred to memory data register. transferred to memory address register . transferred to address bus. incremented by one. transferred to memory data register. transferred to memory address register . transferred to address bus. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Circuit A is a 1-bit adder; circuit B is a 1 bit multiplier.[Hint: Construct the truth table for the adder and the multiplier] Circuit A has the same number of gates as circuit B Circuit B has more gates than circuit A None of these Circuit A has more gates than circuit B Circuit A has the same number of gates as circuit B Circuit B has more gates than circuit A None of these Circuit A has more gates than circuit B ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 P flag is reset when the result has odd parity P flag is set when the result has odd parity P flag is reset when the result has even parity P flag is set when the result has even parity P flag is reset when the result has odd parity P flag is set when the result has odd parity P flag is reset when the result has even parity P flag is set when the result has even parity ANSWER DOWNLOAD EXAMIANS APP
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