Microprocessor During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? T3 OP code fetch T4 OP code fetch T2 OP code fetch T1 OP code fetch T3 OP code fetch T4 OP code fetch T2 OP code fetch T1 OP code fetch ANSWER DOWNLOAD EXAMIANS APP
Microprocessor What is the size (in bytes) of Prefetch queue in 8086? 6. 3. 4. 2. 6. 3. 4. 2. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which one of the following microprocessor is not an 8-bit microprocessor 6502 Z-80 68000 8085 6502 Z-80 68000 8085 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following is not true during the execution of an interrupt service routine, which does not contain any EI instructions the microprocessor can be interrupted by a non-mask able interrupt the microprocessor cannot be interrupted by any mask able interrupt the microprocessor cannot be interrupted by any interrupt all interrupts except non-maskable interrupt are disabled the microprocessor can be interrupted by a non-mask able interrupt the microprocessor cannot be interrupted by any mask able interrupt the microprocessor cannot be interrupted by any interrupt all interrupts except non-maskable interrupt are disabled ANSWER DOWNLOAD EXAMIANS APP
Microprocessor At the beginning of a fetch cycle, the contents of the program counter are transferred to memory address register . incremented by one. transferred to memory data register. transferred to address bus. transferred to memory address register . incremented by one. transferred to memory data register. transferred to address bus. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor S0 and S1 pins are used for acknowledging the interrupt indicating the processor’s status serial communication None of these acknowledging the interrupt indicating the processor’s status serial communication None of these ANSWER DOWNLOAD EXAMIANS APP
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