Microprocessor During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? T1 OP code fetch T4 OP code fetch T2 OP code fetch T3 OP code fetch T1 OP code fetch T4 OP code fetch T2 OP code fetch T3 OP code fetch ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Identify the programmable DMA controller from the following 8251 8279 8257 8253 8251 8279 8257 8253 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor For a memory with a 16-bit address space, the addressability is 8 bits 16 bits 2^16 bits Cannot be determined 8 bits 16 bits 2^16 bits Cannot be determined ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Of the following circuits, the one which involves storage is Mux RS Latch Decoder Nand Mux RS Latch Decoder Nand ANSWER DOWNLOAD EXAMIANS APP
Microprocessor SUB A instruction in 8085 sets zero and carry flags reset carry and sign flags reset zero and parity flags sets zero and sign flags sets zero and carry flags reset carry and sign flags reset zero and parity flags sets zero and sign flags ANSWER DOWNLOAD EXAMIANS APP
Microprocessor If m is a power of 2, the number of select lines required for an m-input mux is: m 2*m log2 (m) 2^m m 2*m log2 (m) 2^m ANSWER DOWNLOAD EXAMIANS APP
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