Microprocessor
During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)?

 T1 OP code fetch
 T3 OP code fetch
 T4 OP code fetch
 T2 OP code fetch

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Microprocessor
How can we make any bit of a register “1”?

 OR that bit with “1” and remaining bits with “0”.
 OR that bit with “0” and remaining bits with “1”.
 AND that bit with “0” and remaining bits with “1”.
 AND that bit with “1” and remaining bits with “0”.

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