Microprocessor During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? T1 OP code fetch T4 OP code fetch T3 OP code fetch T2 OP code fetch T1 OP code fetch T4 OP code fetch T3 OP code fetch T2 OP code fetch ANSWER DOWNLOAD EXAMIANS APP
Microprocessor While STC instruction executes, no flags will be affected. only carry flag will be affected. all flags will be affected. only carry and zero flags will be affected. no flags will be affected. only carry flag will be affected. all flags will be affected. only carry and zero flags will be affected. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor ‘Burst refresh’ in DRAM is also called Concentrated refresh Hidden refresh Distributed refresh None of these Concentrated refresh Hidden refresh Distributed refresh None of these ANSWER DOWNLOAD EXAMIANS APP
Microprocessor What is used to access 16-bit data in 8086? Pipeline architecture. Memory Banking. None of these Data Banking. Pipeline architecture. Memory Banking. None of these Data Banking. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The content of the A15-A8 (higher order address lines) while executing “IN 8-bit port address” instruction are all bits reset (i.e. 00H) all bits set (i.e. FFH) same as the content of A7-A0 irrelevant all bits reset (i.e. 00H) all bits set (i.e. FFH) same as the content of A7-A0 irrelevant ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which language could be used for programming an FPGA. VHDL Verilog Both A and B None VHDL Verilog Both A and B None ANSWER DOWNLOAD EXAMIANS APP
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