Microprocessor Identify the communication interfacing device from the following 8255 8251 8155 8257 8255 8251 8155 8257 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 microprocessor system with memory mapped I/O, which of the following is true? Devices have 8-bit address line Devices are accessed using IN and OUT instructions Arithmetic and logic operations can be directly performed with the I/O data There can be maximum of 256 input devices and 256 output devices Devices have 8-bit address line Devices are accessed using IN and OUT instructions Arithmetic and logic operations can be directly performed with the I/O data There can be maximum of 256 input devices and 256 output devices ANSWER DOWNLOAD EXAMIANS APP
Microprocessor At the beginning of a fetch cycle, the contents of the program counter are transferred to memory address register . transferred to address bus. transferred to memory data register. incremented by one. transferred to memory address register . transferred to address bus. transferred to memory data register. incremented by one. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor HLDA signal in 8085 performs the following operation: Indicates that the CPU has not received the HOLD request. Indicates that another master is requesting the use of the address and data buses. Indicates that the CPU has received the HOLD request and that it will relinquish the bus in the next clock cycle. Hold the data in the accumulator until the microprocessor is turned OFF. Indicates that the CPU has not received the HOLD request. Indicates that another master is requesting the use of the address and data buses. Indicates that the CPU has received the HOLD request and that it will relinquish the bus in the next clock cycle. Hold the data in the accumulator until the microprocessor is turned OFF. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor What are the sets of commands in a program which are not translated into machine instructions during assembly process, called? Directives Operands Mnemonics Identifiers Directives Operands Mnemonics Identifiers ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following interrupt is both level and edge sensitive? TRAP RST 7.5 RST 5.5 INTR TRAP RST 7.5 RST 5.5 INTR ANSWER DOWNLOAD EXAMIANS APP
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