Microprocessor S0 and S1 pins are used for serial communication indicating the processor’s status acknowledging the interrupt None of these serial communication indicating the processor’s status acknowledging the interrupt None of these ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In order to complement the lower nibble of accumulator one can use CMA ORI 0FH ANI 0FH XRI 0FH CMA ORI 0FH ANI 0FH XRI 0FH ANSWER DOWNLOAD EXAMIANS APP
Microprocessor While CMP B instruction executes, all flags will be affected. no flags will be affected. only carry and zero flags will be affected. only carry flag will be affected. all flags will be affected. no flags will be affected. only carry and zero flags will be affected. only carry flag will be affected. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Identify the non-maskable interrupt from the following RST 7.5 RST 4.5 RST 6.5 RST 5.5 RST 7.5 RST 4.5 RST 6.5 RST 5.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following conditions is not allowed in an RS latch? R is asserted, S is asserted R is negated, S is negated R is asserted, S is negated R is negated, S is asserted R is asserted, S is asserted R is negated, S is negated R is asserted, S is negated R is negated, S is asserted ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assuming LSB is at position 0 and MSB at position 7, which bit positions are not used (Undefined) in flag register of an 8085 microprocessor? 1, 3, 4 1, 2, 5 1, 3, 5 2, 3, 5 1, 3, 4 1, 2, 5 1, 3, 5 2, 3, 5 ANSWER DOWNLOAD EXAMIANS APP
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