Microprocessor Which of the following interrupt is both level and edge sensitive? INTR RST 5.5 TRAP RST 7.5 INTR RST 5.5 TRAP RST 7.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The timing difference between a slow memory and fast processor can be resolved if Either A or B Neither A nor B Processor is capable of waiting External buffer is used Either A or B Neither A nor B Processor is capable of waiting External buffer is used ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Monostablemultivibrators (IC74121) are used in a microprocessor based system for frequency measurement. Reason(R): Microprocessor counts the number of interrupt signals/second or within a specified interval through ISR. Both A & R are true and R is the correct explanation of A. Both A & R are true but R is not the correct explanation of A. A is true but R is false. A is false but R is true. Both A & R are true and R is the correct explanation of A. Both A & R are true but R is not the correct explanation of A. A is true but R is false. A is false but R is true. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor When any data transfer instruction, to transfer the data from memory to microprocessor, is executed the condition flags are always set always reset affected indicating specific conditions not affected always set always reset affected indicating specific conditions not affected ANSWER DOWNLOAD EXAMIANS APP
Microprocessor What is used to access 16-bit data in 8086? Memory Banking. Pipeline architecture. Data Banking. None of these Memory Banking. Pipeline architecture. Data Banking. None of these ANSWER DOWNLOAD EXAMIANS APP
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