Microprocessor Which of the following interrupt is both level and edge sensitive? RST 7.5 TRAP RST 5.5 INTR RST 7.5 TRAP RST 5.5 INTR ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following conditions is not allowed in an RS latch? R is asserted, S is negated R is asserted, S is asserted R is negated, S is negated R is negated, S is asserted R is asserted, S is negated R is asserted, S is asserted R is negated, S is negated R is negated, S is asserted ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The microprocessor may be made to exit from HALT state by asserting any of the five interrupt lines READY line RESTART A or B or HOLD line any of the five interrupt lines READY line RESTART A or B or HOLD line ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A bus connected between the CPU and main memory that permits transfer of information between main memory and the CPU is known as Address bus Control bus Memory bus DMA bus Address bus Control bus Memory bus DMA bus ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The address bus width of a microprocessor which is capable of addressing 64 Kbytes of the memory is 16 8 20 12 16 8 20 12 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The number of hardware interrupts present in 8085 microprocessor are 10 16 8 5 10 16 8 5 ANSWER DOWNLOAD EXAMIANS APP
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