Microprocessor Which of the following interrupt is both level and edge sensitive? INTR TRAP RST 7.5 RST 5.5 INTR TRAP RST 7.5 RST 5.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The output data lines of microprocessor and memories are usually tristated because More than one device can transmit over the data bus at the same time The data line can be multiplexed for both input and output It increases the speed of data transfer over the data bus More than one device can transmit information over the data bus by enabling only one device at a time More than one device can transmit over the data bus at the same time The data line can be multiplexed for both input and output It increases the speed of data transfer over the data bus More than one device can transmit information over the data bus by enabling only one device at a time ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following conditions is not allowed in an RS latch? R is negated, S is asserted R is asserted, S is asserted R is asserted, S is negated R is negated, S is negated R is negated, S is asserted R is asserted, S is asserted R is asserted, S is negated R is negated, S is negated ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The clock speed of 8085 is 3.2MHz. 1KHz. 1MHz. 3.2KHz. 3.2MHz. 1KHz. 1MHz. 3.2KHz. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During the execution of the instruction, the ________tests the status and control flags and updates them based on the results of executing the instruction. Bus Interface Unit (BIU) Execution Unit (EU) None of these Both ‘c’ and ‘d’ Bus Interface Unit (BIU) Execution Unit (EU) None of these Both ‘c’ and ‘d’ ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 name/names of the 16 bit registers is/are stack pointer. both A and B. program counter. none of these. stack pointer. both A and B. program counter. none of these. ANSWER DOWNLOAD EXAMIANS APP
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