Microprocessor Which of the following interrupt is both level and edge sensitive? RST 5.5 RST 7.5 INTR TRAP RST 5.5 RST 7.5 INTR TRAP ANSWER DOWNLOAD EXAMIANS APP
Microprocessor An 8-bit microprocessor can have ………….. address lines. 16 8 cannot be predicted 32 16 8 cannot be predicted 32 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Consider the following statements: In 8085 microprocessor, data-bus and address bus are multiplexed in order to I)Increase the speed of microprocessor. II)Reduce the number of pins. III)Connect more peripheral chips. Which of these statements is/are correct? (I) only (I), (II) & (III) (II) only (II) & (III) (I) only (I), (II) & (III) (II) only (II) & (III) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor When an 8085 microprocessor is reset, the address bus contains 0043H 0000H 002CH 003CH 0043H 0000H 002CH 003CH ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The instruction set of a microprocessor cannot be changed by the user is specified by the user is specified by the manufacturers is stored inside the microprocessor cannot be changed by the user is specified by the user is specified by the manufacturers is stored inside the microprocessor ANSWER DOWNLOAD EXAMIANS APP
Microprocessor While STC instruction executes, no flags will be affected. all flags will be affected. only carry and zero flags will be affected. only carry flag will be affected. no flags will be affected. all flags will be affected. only carry and zero flags will be affected. only carry flag will be affected. ANSWER DOWNLOAD EXAMIANS APP
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