Microprocessor Which of the following interrupt is both level and edge sensitive? TRAP INTR RST 5.5 RST 7.5 TRAP INTR RST 5.5 RST 7.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor At the beginning of a fetch cycle, the contents of the program counter are transferred to memory data register. transferred to address bus. transferred to memory address register . incremented by one. transferred to memory data register. transferred to address bus. transferred to memory address register . incremented by one. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The interrupt facility is provided in microprocessor to stop the microprocessor when desired keep a control on the working of the microprocessor stop the microprocessor when it starts malfunctioning change the sequence of the instructions being executed stop the microprocessor when desired keep a control on the working of the microprocessor stop the microprocessor when it starts malfunctioning change the sequence of the instructions being executed ANSWER DOWNLOAD EXAMIANS APP
Microprocessor S0 and S1 pins are used for indicating the processor’s status acknowledging the interrupt serial communication None of these indicating the processor’s status acknowledging the interrupt serial communication None of these ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A microprocessor with a 12-bit address bus will be able to access 4 K bytes 10 K bytes 1 K bytes 8 K bytes 4 K bytes 10 K bytes 1 K bytes 8 K bytes ANSWER DOWNLOAD EXAMIANS APP
Microprocessor SUB A instruction in 8085 reset carry and sign flags reset zero and parity flags sets zero and carry flags sets zero and sign flags reset carry and sign flags reset zero and parity flags sets zero and carry flags sets zero and sign flags ANSWER DOWNLOAD EXAMIANS APP
EXAMIANS