Microprocessor Which of the following interrupt is both level and edge sensitive? RST 5.5 RST 7.5 TRAP INTR RST 5.5 RST 7.5 TRAP INTR ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The microprocessor may be made to exit from HALT state by asserting RESTART A or B or HOLD line READY line any of the five interrupt lines RESTART A or B or HOLD line READY line any of the five interrupt lines ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A combinational PLD with a fixed AND array and a programmable OR array is called a PLD PAL PROM PLA PLD PAL PROM PLA ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The data lines of 8085 microprocessor are multiplexed with status lines lower order address lines higher order address lines None of these status lines lower order address lines higher order address lines None of these ANSWER DOWNLOAD EXAMIANS APP
Microprocessor RST0 - RST7 are the __________ in 8085. conditional interrupts software interrupts logical interrupts hardware interrupts conditional interrupts software interrupts logical interrupts hardware interrupts ANSWER DOWNLOAD EXAMIANS APP
Microprocessor What is the size (in bytes) of Prefetch queue in 8086? 2. 4. 3. 6. 2. 4. 3. 6. ANSWER DOWNLOAD EXAMIANS APP
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