Microprocessor Which of the following interrupt is both level and edge sensitive? RST 7.5 INTR TRAP RST 5.5 RST 7.5 INTR TRAP RST 5.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor ________used to implement the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by setting various bits to form masks or generate output data via the Serial Output Data (SOD) line. EI DI SIM RIM EI DI SIM RIM ANSWER DOWNLOAD EXAMIANS APP
Microprocessor DS directive in 8085 None of these Forces the assembler to reserve a specified number of consecutive bytes in the memory Forces the assembler to reserve one byte of memory Forces the assembler to reserve a specified number of bytes in the memory None of these Forces the assembler to reserve a specified number of consecutive bytes in the memory Forces the assembler to reserve one byte of memory Forces the assembler to reserve a specified number of bytes in the memory ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The interrupt facility is provided in microprocessor to keep a control on the working of the microprocessor stop the microprocessor when desired stop the microprocessor when it starts malfunctioning change the sequence of the instructions being executed keep a control on the working of the microprocessor stop the microprocessor when desired stop the microprocessor when it starts malfunctioning change the sequence of the instructions being executed ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Monostablemultivibrators (IC74121) are used in a microprocessor based system for frequency measurement. Reason(R): Microprocessor counts the number of interrupt signals/second or within a specified interval through ISR. A is true but R is false. Both A & R are true but R is not the correct explanation of A. A is false but R is true. Both A & R are true and R is the correct explanation of A. A is true but R is false. Both A & R are true but R is not the correct explanation of A. A is false but R is true. Both A & R are true and R is the correct explanation of A. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following conditions is not allowed in an RS latch? R is negated, S is asserted R is asserted, S is asserted R is asserted, S is negated R is negated, S is negated R is negated, S is asserted R is asserted, S is asserted R is asserted, S is negated R is negated, S is negated ANSWER DOWNLOAD EXAMIANS APP
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