Microprocessor Which of the following interrupt is both level and edge sensitive? INTR RST 5.5 TRAP RST 7.5 INTR RST 5.5 TRAP RST 7.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor DS directive in 8085 None of these Forces the assembler to reserve a specified number of consecutive bytes in the memory Forces the assembler to reserve one byte of memory Forces the assembler to reserve a specified number of bytes in the memory None of these Forces the assembler to reserve a specified number of consecutive bytes in the memory Forces the assembler to reserve one byte of memory Forces the assembler to reserve a specified number of bytes in the memory ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The address bus of any microprocessor is always Unidirectional Either unidirectional or bi-directional Bi-directional None Unidirectional Either unidirectional or bi-directional Bi-directional None ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following statements for intel 8085 is correct? PC specifies the address of the instruction being executed Program Counter (PC) specifies the address of the instruction last executed PC specifies the address of the instruction to be executed PC specifies the number of instructions executed so far PC specifies the address of the instruction being executed Program Counter (PC) specifies the address of the instruction last executed PC specifies the address of the instruction to be executed PC specifies the number of instructions executed so far ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion (A): Negative values of incremental operator in DO loop are allowed in Fortran 77 but not in earlier versions of Fortran. Reason (R): Fortran 77 has better array facilities than earlier versions of Fortran. Both A and R are correct and R is correct explanation of A A is wrong R is correct Both A and R are correct but R is not correct explanation of A A is correct R is wrong Both A and R are correct and R is correct explanation of A A is wrong R is correct Both A and R are correct but R is not correct explanation of A A is correct R is wrong ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. Bus Interface Unit (BIU) None of these Both ‘b’ and ‘c’ Execution Unit (EU) Bus Interface Unit (BIU) None of these Both ‘b’ and ‘c’ Execution Unit (EU) ANSWER DOWNLOAD EXAMIANS APP
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