Microprocessor Which of the following interrupt is both level and edge sensitive? RST 5.5 TRAP RST 7.5 INTR RST 5.5 TRAP RST 7.5 INTR ANSWER DOWNLOAD EXAMIANS APP
Microprocessor If the number of address bits in a memory is reduced by 2 and the addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory) Remains unchanged Increases by 2^(address bits)/addressability Doubles Halves Remains unchanged Increases by 2^(address bits)/addressability Doubles Halves ANSWER DOWNLOAD EXAMIANS APP
Microprocessor When any data transfer instruction, to transfer the data from memory to microprocessor, is executed the condition flags are affected indicating specific conditions always reset always set not affected affected indicating specific conditions always reset always set not affected ANSWER DOWNLOAD EXAMIANS APP
Microprocessor RST0 - RST7 are the __________ in 8085. logical interrupts hardware interrupts software interrupts conditional interrupts logical interrupts hardware interrupts software interrupts conditional interrupts ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Inintel 8085A microprocessor ALE signal is made high to Enable the data bus to be used as low order address bus To latch data D0-D7 from data bus To disable data bus To achieve all the functions listed above Enable the data bus to be used as low order address bus To latch data D0-D7 from data bus To disable data bus To achieve all the functions listed above ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Identify the non-maskable interrupt from the following RST 7.5 RST 5.5 RST 6.5 RST 4.5 RST 7.5 RST 5.5 RST 6.5 RST 4.5 ANSWER DOWNLOAD EXAMIANS APP
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