Microprocessor Which of the following interrupt is both level and edge sensitive? RST 5.5 INTR RST 7.5 TRAP RST 5.5 INTR RST 7.5 TRAP ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The instruction set of a microprocessor is specified by the user cannot be changed by the user is stored inside the microprocessor is specified by the manufacturers is specified by the user cannot be changed by the user is stored inside the microprocessor is specified by the manufacturers ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The number of hardware interrupts present in 8085 microprocessor are 8 10 16 5 8 10 16 5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor We say that a set of gates is logically complete if we can build any circuit without using any other kind of gates. Which of the following sets are logically complete Set of {AND,OR} Set of {AND,OR,NOT} None of these Set of {EXOR, NOT} Set of {AND,OR} Set of {AND,OR,NOT} None of these Set of {EXOR, NOT} ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion (A): Each memory chip has its own address latch. Reason (R): ALE signal comes out of microprocessor 8085 and goes to memory chip. A is correct R is wrong Both A and R are correct and R is correct explanation of A Both A and R are correct but R is not correct explanation of A A is wrong R is correct A is correct R is wrong Both A and R are correct and R is correct explanation of A Both A and R are correct but R is not correct explanation of A A is wrong R is correct ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? T4 OP code fetch T1 OP code fetch T3 OP code fetch T2 OP code fetch T4 OP code fetch T1 OP code fetch T3 OP code fetch T2 OP code fetch ANSWER DOWNLOAD EXAMIANS APP
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