Microprocessor Which of the following interrupt is both level and edge sensitive? INTR RST 5.5 TRAP RST 7.5 INTR RST 5.5 TRAP RST 7.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor While INX B instruction execute, all flags will be affected only carry flag will be affected no flags will be affected only carry and zero flags will be affected all flags will be affected only carry flag will be affected no flags will be affected only carry and zero flags will be affected ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During the execution of the instruction, the ________tests the status and control flags and updates them based on the results of executing the instruction. Bus Interface Unit (BIU) None of these Both ‘c’ and ‘d’ Execution Unit (EU) Bus Interface Unit (BIU) None of these Both ‘c’ and ‘d’ Execution Unit (EU) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Identify the non-maskable interrupt from the following RST 6.5 RST 4.5 RST 5.5 RST 7.5 RST 6.5 RST 4.5 RST 5.5 RST 7.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor CALL instruction is a ______ instruction. 1 bytes 2 bytes 3 bytes 4 bytes 1 bytes 2 bytes 3 bytes 4 bytes ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion (A): Each memory chip has its own address latch. Reason (R): ALE signal comes out of microprocessor 8085 and goes to memory chip. Both A and R are correct and R is correct explanation of A Both A and R are correct but R is not correct explanation of A A is correct R is wrong A is wrong R is correct Both A and R are correct and R is correct explanation of A Both A and R are correct but R is not correct explanation of A A is correct R is wrong A is wrong R is correct ANSWER DOWNLOAD EXAMIANS APP
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