Microprocessor Which of the following interrupt is both level and edge sensitive? RST 7.5 INTR TRAP RST 5.5 RST 7.5 INTR TRAP RST 5.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following pair of gates can form a latch? A pair of cross coupled OR A pair of cross copled AND A pair of cross coupled NAND A cross coupled NAND/OR A pair of cross coupled OR A pair of cross copled AND A pair of cross coupled NAND A cross coupled NAND/OR ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In an 8085 microprocessor based system, the contents of SP are 2000H. POP H instruction will transfer the contents of memory location 2000H and 1999H to H and L registers respectively 2000H and 1FFFH to H and L registers respectively 2001H and 2002H to H and L registers respectively 2001H and 2000H to H and L registers respectively 2000H and 1999H to H and L registers respectively 2000H and 1FFFH to H and L registers respectively 2001H and 2002H to H and L registers respectively 2001H and 2000H to H and L registers respectively ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The number of hardware interrupts present in 8085 microprocessor are 5 16 10 8 5 16 10 8 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The relation among IC (Instruction Cycle), FC (Fetch cycle) and EC (Execute Cycle) is IC = FC - EC IC = FC + EC IC = FC + 2EC EC = IC + FC IC = FC - EC IC = FC + EC IC = FC + 2EC EC = IC + FC ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The execution of RST n instruction causes the stack pointer to None of these remain unaffected decrement by two increment by two None of these remain unaffected decrement by two increment by two ANSWER DOWNLOAD EXAMIANS APP
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