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Microprocessor

Microprocessor
Which of the following interrupt is both level and edge sensitive?

 RST 7.5
 TRAP
 RST 5.5
 INTR

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Microprocessor
In an intel 8085A, which is the first machine cycle of an instruction?

 An op-code fetch cycle
 A memory read cycle
 A memory write cycle
 An I/O read cycle

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Microprocessor
The timing difference between a slow memory and fast processor can be resolved if

External buffer is used
Either A or B
Processor is capable of waiting
Neither A nor B

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Microprocessor
The number of status flags present in 8085 microprocessor are

 5
 8
 10
 16

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Microprocessor
The microprocessor issues ALE during first T-state of

 every machine cycle
 fetch cycle only
 memory WRITE cycle only
 memory READ cycle only

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Microprocessor
Which one of the following interrupt/interrupts is/are only level triggering?

 RST 6.5
 RST 5.5
 TRAP
 both ‘a’ and ‘b’

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