Microprocessor Which of the following interrupt is both level and edge sensitive? TRAP RST 7.5 RST 5.5 INTR TRAP RST 7.5 RST 5.5 INTR ANSWER DOWNLOAD EXAMIANS APP
Microprocessor ________used to implement the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by setting various bits to form masks or generate output data via the Serial Output Data (SOD) line. SIM RIM DI EI SIM RIM DI EI ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assuming LSB is at position 0 and MSB at position 7, which bit positions are not used (Undefined) in flag register of an 8085 microprocessor? 1, 2, 5 1, 3, 4 1, 3, 5 2, 3, 5 1, 2, 5 1, 3, 4 1, 3, 5 2, 3, 5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which one of the following instruction may be used to clear the accumulator content irrespective of its initial value? ORA A CLR A SUB A MOV A, 00H ORA A CLR A SUB A MOV A, 00H ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Ready pin of microprocessor is used to provide direct memory access to introduce wait state to indicate that microprocessor is ready to receive inputs to indicate that microprocessor is ready to receive outputs to provide direct memory access to introduce wait state to indicate that microprocessor is ready to receive inputs to indicate that microprocessor is ready to receive outputs ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During the execution of the instruction, the ________tests the status and control flags and updates them based on the results of executing the instruction. Execution Unit (EU) Bus Interface Unit (BIU) Both ‘c’ and ‘d’ None of these Execution Unit (EU) Bus Interface Unit (BIU) Both ‘c’ and ‘d’ None of these ANSWER DOWNLOAD EXAMIANS APP
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