Which of the following interrupt is both level and edge sensitive?

Microprocessor
Which of the following interrupt is both level and edge sensitive?

RST 7.5

TRAP

RST 5.5

INTR

RST 7.5

TRAP

RST 5.5

INTR

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Microprocessor
If the number of address bits in a memory is reduced by 2 and the addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory)

Increases by 2^(address bits)/addressability

Halves

Remains unchanged

Doubles

Increases by 2^(address bits)/addressability

Halves

Remains unchanged

Doubles

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Microprocessor
When RET instruction is executed by any subroutine then

the top of the stack will be popped out and assigned to the PC.

the PC will be incremented after the execution of the instruction.

without any operation, the calling program would resume from instruction immediately following the call instruction.

without any operation, the calling program would resume from instruction immediately following the call instruction and also the PC will be incremented after the execution of the instruction.

the top of the stack will be popped out and assigned to the PC.

the PC will be incremented after the execution of the instruction.

without any operation, the calling program would resume from instruction immediately following the call instruction.

without any operation, the calling program would resume from instruction immediately following the call instruction and also the PC will be incremented after the execution of the instruction.

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Microprocessor
Which of the following statements for intel 8085 is correct?

PC specifies the number of instructions executed so far

PC specifies the address of the instruction to be executed

Program Counter (PC) specifies the address of the instruction last executed

PC specifies the address of the instruction being executed

PC specifies the number of instructions executed so far

PC specifies the address of the instruction to be executed

Program Counter (PC) specifies the address of the instruction last executed

PC specifies the address of the instruction being executed

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Microprocessor
Consider the following I) Sign flag II) Trap flag III) Parity flag IV) Auxiliary carry flag. Which one of the above flags is/are present in 8085 microprocessor?

(I) only

(II) & (III)

(I) ,(III) & (IV)

(I) & (II)

(I) only

(II) & (III)

(I) ,(III) & (IV)

(I) & (II)

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Microprocessor
The interrupt facility is provided in microprocessor to

change the sequence of the instructions being executed

stop the microprocessor when desired

stop the microprocessor when it starts malfunctioning

keep a control on the working of the microprocessor

change the sequence of the instructions being executed

stop the microprocessor when desired

stop the microprocessor when it starts malfunctioning

keep a control on the working of the microprocessor

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Microprocessor

Microprocessor Which of the following interrupt is both level and edge sensitive?

Microprocessor If the number of address bits in a memory is reduced by 2 and the addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory)

Microprocessor When RET instruction is executed by any subroutine then

Microprocessor Which of the following statements for intel 8085 is correct?

Microprocessor Consider the following I) Sign flag II) Trap flag III) Parity flag IV) Auxiliary carry flag. Which one of the above flags is/are present in 8085 microprocessor?

Microprocessor The interrupt facility is provided in microprocessor to

Microprocessor
Which of the following interrupt is both level and edge sensitive?

Microprocessor
If the number of address bits in a memory is reduced by 2 and the addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory)

Microprocessor
When RET instruction is executed by any subroutine then

Microprocessor
Which of the following statements for intel 8085 is correct?

Microprocessor
Consider the following I) Sign flag II) Trap flag III) Parity flag IV) Auxiliary carry flag. Which one of the above flags is/are present in 8085 microprocessor?

Microprocessor
The interrupt facility is provided in microprocessor to