Microprocessor During OPCODE fetch the state of S0 and S1 is 01 00 11 10 01 00 11 10 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following pair of gates can form a latch? A pair of cross coupled NAND A pair of cross coupled OR A cross coupled NAND/OR A pair of cross copled AND A pair of cross coupled NAND A pair of cross coupled OR A cross coupled NAND/OR A pair of cross copled AND ANSWER DOWNLOAD EXAMIANS APP
Microprocessor While INX B instruction execute, no flags will be affected all flags will be affected only carry flag will be affected only carry and zero flags will be affected no flags will be affected all flags will be affected only carry flag will be affected only carry and zero flags will be affected ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Ready signal of microprocessor is used to detect whether a peripheral is ready for the data transfer or not. Reason(R): In the microprocessor during data transfer operations, the wait states are added by forcing the ready signal low. Both A & R are true and R is the correct explanation of A. A is true but R is false. A is false but R is true. Both A & R are true but R is not the correct explanation of A . Both A & R are true and R is the correct explanation of A. A is true but R is false. A is false but R is true. Both A & R are true but R is not the correct explanation of A . ANSWER DOWNLOAD EXAMIANS APP
Microprocessor XCHG instruction exchanges the content of H-L with ______ register pair. Stack Pointer B-C PSW D-E Stack Pointer B-C PSW D-E ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Identify the non-programmable interfacing device from the following 8212. 8295. 8257. 8255. 8212. 8295. 8257. 8255. ANSWER DOWNLOAD EXAMIANS APP
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