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Microprocessor

Microprocessor
During OPCODE fetch the state of S0 and S1 is

 00
 11
 01
 10

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Microprocessor
For a memory with a 16-bit address space, the addressability is

8 bits
16 bits
Cannot be determined
2^16 bits

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Microprocessor
Which of the following conditions is not allowed in an RS latch?

R is negated, S is negated
R is negated, S is asserted
R is asserted, S is negated
R is asserted, S is asserted

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Microprocessor
Pick out the matching pair

 S0;S1;wait status
 READY; RIM
 HOLD; DMA
 SID; SIM

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Microprocessor
DMA signal/signals in 8085 is/are

 HLDA.
 All.
 READY.
 HOLD.

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Microprocessor
During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)?

 T1 OP code fetch
 T2 OP code fetch
 T3 OP code fetch
 T4 OP code fetch

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