Microprocessor During OPCODE fetch the state of S0 and S1 is 00 11 01 10 00 11 01 10 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Address bus is unidirectional. Reason(R): Data bus is bidirectional Both A & R are true but R is not the correct explanation of A A is false but R is true A is true but R is false Both A & R are true and R is the correct explanation of A Both A & R are true but R is not the correct explanation of A A is false but R is true A is true but R is false Both A & R are true and R is the correct explanation of A ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The addressing mode in instruction PUSH B is immediate register register indirect direct immediate register register indirect direct ANSWER DOWNLOAD EXAMIANS APP
Microprocessor What is the size (in bytes) of Prefetch queue in 8086? 2. 4. 3. 6. 2. 4. 3. 6. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 microprocessor, the RST6 instruction transfer programme execution to following location 0024H. 0048H. 0030H. 0060H. 0024H. 0048H. 0030H. 0060H. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor PUSH B instruction in 8085 microprocessor causes registers B & C to be cleared the contents of register B only to be copied in the stack the contents of register B & C to be copied in the stack the contents of registers B & C to be transferred in the stack and and the registers get cleared registers B & C to be cleared the contents of register B only to be copied in the stack the contents of register B & C to be copied in the stack the contents of registers B & C to be transferred in the stack and and the registers get cleared ANSWER DOWNLOAD EXAMIANS APP
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