Microprocessor
Assertion(A): Ready signal of microprocessor is used to detect whether a peripheral is ready for the data transfer or not. Reason(R): In the microprocessor during data transfer operations, the wait states are added by forcing the ready signal low.

 A is false but R is true.
 Both A & R are true but R is not the correct explanation of A .
 A is true but R is false.
 Both A & R are true and R is the correct explanation of A.

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Microprocessor
Cycle stealing mode of DMA operation involves

 Data transfer takes place between the I/O device and memory during every alternate clock cycle
 The DMA control waiting for the microprocessor to finish execution of the program and then takes over the buses
 While the microprocessor is executing a program an interface circuit takes over control of address, data, control buses when not in use by microprocessor
 DMA controller taking over the address, data and control buses while a block of data is transferred between memory and I/O device

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