Microprocessor During OPCODE fetch the state of S0 and S1 is 10 11 01 00 10 11 01 00 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor SPHL instruction copies the content of H-L register pair to the _________. B-C Stack Pointer PSW D-E B-C Stack Pointer PSW D-E ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The correct sequence of steps in the instruction cycle of a basic computer is Fetch, Decode, Read effective address and, Execute. Fetch, Read effective address, Decode and Execute. Fetch, Execute, Decode and Read effective address. Read effective address, Decode, Fetch and Execute. Fetch, Decode, Read effective address and, Execute. Fetch, Read effective address, Decode and Execute. Fetch, Execute, Decode and Read effective address. Read effective address, Decode, Fetch and Execute. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following conditions is not allowed in an RS latch? R is asserted, S is negated R is negated, S is negated R is asserted, S is asserted R is negated, S is asserted R is asserted, S is negated R is negated, S is negated R is asserted, S is asserted R is negated, S is asserted ANSWER DOWNLOAD EXAMIANS APP
Microprocessor What is the size (in bytes) of Prefetch queue in 8086? 3. 6. 4. 2. 3. 6. 4. 2. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 microprocessor, the RST6 instruction transfer programme execution to following location 0048H. 0030H. 0060H. 0024H. 0048H. 0030H. 0060H. 0024H. ANSWER DOWNLOAD EXAMIANS APP
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