Microprocessor During OPCODE fetch the state of S0 and S1 is 01 11 00 10 01 11 00 10 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Identify the non-programmable interfacing device from the following 8295. 8212. 8257. 8255. 8295. 8212. 8257. 8255. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The cycle required to fetch and execute an instruction in a 8085 microprocessor is which one of the following? Instruction cycle Clock cycle Memory cycle Machine cycle Instruction cycle Clock cycle Memory cycle Machine cycle ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? T1 OP code fetch T2 OP code fetch T4 OP code fetch T3 OP code fetch T1 OP code fetch T2 OP code fetch T4 OP code fetch T3 OP code fetch ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following instruction is not possible in 8085? POP B POP D POP 30 H POP PSW POP B POP D POP 30 H POP PSW ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which one of the following interrupt/interrupts is/are only level triggering? both ‘a’ and ‘b’ RST 6.5 RST 5.5 TRAP both ‘a’ and ‘b’ RST 6.5 RST 5.5 TRAP ANSWER DOWNLOAD EXAMIANS APP
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