Microprocessor During OPCODE fetch the state of S0 and S1 is 00 10 11 01 00 10 11 01 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Let the content of accumulator and register B be 0000 0100 and 0100 0000 respectively before execution of instruction SUB B. The content of accumulator after the execution of this instruction will be 11000100 00000100 01000000 010001000 11000100 00000100 01000000 010001000 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assuming LSB is at position 0 and MSB at position 7, which bit positions are not used (Undefined) in flag register of an 8085 microprocessor? 1, 2, 5 1, 3, 4 1, 3, 5 2, 3, 5 1, 2, 5 1, 3, 4 1, 3, 5 2, 3, 5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor DMA signal/signals in 8085 is/are READY. HOLD. HLDA. All. READY. HOLD. HLDA. All. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following interrupt is both level and edge sensitive? RST 7.5 RST 5.5 TRAP INTR RST 7.5 RST 5.5 TRAP INTR ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085, the pins for SID and SOD are 4 and 5 respectively 5 and 4 respectively 3 and 4 respectively 4 and 3 respectively 4 and 5 respectively 5 and 4 respectively 3 and 4 respectively 4 and 3 respectively ANSWER DOWNLOAD EXAMIANS APP
EXAMIANS