Microprocessor During OPCODE fetch the state of S0 and S1 is 01 00 10 11 01 00 10 11 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A combinational PLD with a fixed AND array and a programmable OR array is called a PLA PLD PROM PAL PLA PLD PROM PAL ANSWER DOWNLOAD EXAMIANS APP
Microprocessor What is the size (in bytes) of Prefetch queue in 8086? 2. 6. 4. 3. 2. 6. 4. 3. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor SUB A instruction in 8085 sets zero and sign flags reset carry and sign flags sets zero and carry flags reset zero and parity flags sets zero and sign flags reset carry and sign flags sets zero and carry flags reset zero and parity flags ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? T4 OP code fetch T3 OP code fetch T2 OP code fetch T1 OP code fetch T4 OP code fetch T3 OP code fetch T2 OP code fetch T1 OP code fetch ANSWER DOWNLOAD EXAMIANS APP
Microprocessor How can we make any bit of a register “0”? OR that bit with “0” and remaining bits with “1”. AND that bit with “0” and remaining bits with “1”. OR that bit with “1” and remaining bits with “0”. AND that bit with “1” and remaining bits with “0”. OR that bit with “0” and remaining bits with “1”. AND that bit with “0” and remaining bits with “1”. OR that bit with “1” and remaining bits with “0”. AND that bit with “1” and remaining bits with “0”. ANSWER DOWNLOAD EXAMIANS APP
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