Microprocessor During OPCODE fetch the state of S0 and S1 is 01 10 11 00 01 10 11 00 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The interrupt facility is provided in microprocessor to stop the microprocessor when desired stop the microprocessor when it starts malfunctioning keep a control on the working of the microprocessor change the sequence of the instructions being executed stop the microprocessor when desired stop the microprocessor when it starts malfunctioning keep a control on the working of the microprocessor change the sequence of the instructions being executed ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The correct sequence of steps in the instruction cycle of a basic computer is Read effective address, Decode, Fetch and Execute. Fetch, Decode, Read effective address and, Execute. Fetch, Execute, Decode and Read effective address. Fetch, Read effective address, Decode and Execute. Read effective address, Decode, Fetch and Execute. Fetch, Decode, Read effective address and, Execute. Fetch, Execute, Decode and Read effective address. Fetch, Read effective address, Decode and Execute. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Consider the following registers: 1. Accumulator and flag register 2. B and C register 3. D and E register 4. H and L register Which of these 8-bit registers of 8085 microprocessor can be paired together to make a 16-bit register? 1, 2 and 4 2, 3 and 4 1, 2 and 3 1, 3 and 4 1, 2 and 4 2, 3 and 4 1, 2 and 3 1, 3 and 4 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The timing difference between a slow memory and fast processor can be resolved if Processor is capable of waiting Neither A nor B External buffer is used Either A or B Processor is capable of waiting Neither A nor B External buffer is used Either A or B ANSWER DOWNLOAD EXAMIANS APP
Microprocessor RST 3 instruction will cause the processor to branch to the location 0024H 0028H 0018H 0000H 0024H 0028H 0018H 0000H ANSWER DOWNLOAD EXAMIANS APP
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