Microprocessor During OPCODE fetch the state of S0 and S1 is 11 00 10 01 11 00 10 01 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The content of the A15-A8 (higher order address lines) while executing “IN 8-bit port address” instruction are irrelevant same as the content of A7-A0 all bits set (i.e. FFH) all bits reset (i.e. 00H) irrelevant same as the content of A7-A0 all bits set (i.e. FFH) all bits reset (i.e. 00H) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Ready signal of microprocessor is used to detect whether a peripheral is ready for the data transfer or not. Reason(R): In the microprocessor during data transfer operations, the wait states are added by forcing the ready signal low. Both A & R are true but R is not the correct explanation of A . Both A & R are true and R is the correct explanation of A. A is false but R is true. A is true but R is false. Both A & R are true but R is not the correct explanation of A . Both A & R are true and R is the correct explanation of A. A is false but R is true. A is true but R is false. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following interrupt is both level and edge sensitive? RST 5.5 TRAP RST 7.5 INTR RST 5.5 TRAP RST 7.5 INTR ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 microprocessor which one of the following statement is wrong there is a pin available for serial output serial I/O is not possible serial I/O is possible through SIM and RIM instruction there is a pin available for serial input there is a pin available for serial output serial I/O is not possible serial I/O is possible through SIM and RIM instruction there is a pin available for serial input ANSWER DOWNLOAD EXAMIANS APP
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