Microprocessor HLDA signal in 8085 performs the following operation: Indicates that the CPU has received the HOLD request and that it will relinquish the bus in the next clock cycle. Indicates that another master is requesting the use of the address and data buses. Hold the data in the accumulator until the microprocessor is turned OFF. Indicates that the CPU has not received the HOLD request. Indicates that the CPU has received the HOLD request and that it will relinquish the bus in the next clock cycle. Indicates that another master is requesting the use of the address and data buses. Hold the data in the accumulator until the microprocessor is turned OFF. Indicates that the CPU has not received the HOLD request. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 microprocessor which one of the following statement is wrong serial I/O is possible through SIM and RIM instruction there is a pin available for serial output serial I/O is not possible there is a pin available for serial input serial I/O is possible through SIM and RIM instruction there is a pin available for serial output serial I/O is not possible there is a pin available for serial input ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 P flag is set when the result has odd parity P flag is reset when the result has odd parity P flag is set when the result has even parity P flag is reset when the result has even parity P flag is set when the result has odd parity P flag is reset when the result has odd parity P flag is set when the result has even parity P flag is reset when the result has even parity ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Consider the following registers: 1. Accumulator and flag register 2. B and C register 3. D and E register 4. H and L register Which of these 8-bit registers of 8085 microprocessor can be paired together to make a 16-bit register? 1, 2 and 3 2, 3 and 4 1, 3 and 4 1, 2 and 4 1, 2 and 3 2, 3 and 4 1, 3 and 4 1, 2 and 4 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? T2 OP code fetch T4 OP code fetch T3 OP code fetch T1 OP code fetch T2 OP code fetch T4 OP code fetch T3 OP code fetch T1 OP code fetch ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The first machine cycle of an instruction is always An I/O read cycle A memory write cycle A memory read cycle A fetch cycle An I/O read cycle A memory write cycle A memory read cycle A fetch cycle ANSWER DOWNLOAD EXAMIANS APP
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