Microprocessor Which one of the following interrupt/interrupts is/are only level triggering? RST 6.5 RST 5.5 both ‘a’ and ‘b’ TRAP RST 6.5 RST 5.5 both ‘a’ and ‘b’ TRAP ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following instruction will never affect the zero flag? DCR R DCX Rp XRA R ORA R DCR R DCX Rp XRA R ORA R ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 microprocessor based system maximum possible number of input/output devices can be connected using I/O mapped I/O technique is 65536 64 512 256 65536 64 512 256 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor If the number of address bits in a memory is reduced by 2 and the addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory) Doubles Increases by 2^(address bits)/addressability Halves Remains unchanged Doubles Increases by 2^(address bits)/addressability Halves Remains unchanged ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A mask programmed ROM is programmed by the user erasable and programmable erasable electrically programmed at the time of fabrication programmed by the user erasable and programmable erasable electrically programmed at the time of fabrication ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 which addressing mode is also called inherent addressing? Direct Register Immediate Implicit Direct Register Immediate Implicit ANSWER DOWNLOAD EXAMIANS APP
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