Microprocessor Which one of the following interrupt/interrupts is/are only level triggering? RST 5.5 RST 6.5 both ‘a’ and ‘b’ TRAP RST 5.5 RST 6.5 both ‘a’ and ‘b’ TRAP ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Because we wish to allow each ASCII code to occupy one location in memory, most memories are __________ addressable. DOUBLEWORD (32 bits) WORD (16 bits) NIBBLE BYTE DOUBLEWORD (32 bits) WORD (16 bits) NIBBLE BYTE ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The address bus width of a microprocessor which is capable of addressing 64 Kbytes of the memory is 8 12 16 20 8 12 16 20 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the data transfer is not possible in microprocessor memory to accumulator I/O device to accumulator memory to memory accumulator to memory memory to accumulator I/O device to accumulator memory to memory accumulator to memory ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The operating modes of 8255 A are called Mode 0 and mode 2 Mode 0, mode 1 and mode 2 Mode 0 and mode 1 Mode 0, mode 2 and mode 3 Mode 0 and mode 2 Mode 0, mode 1 and mode 2 Mode 0 and mode 1 Mode 0, mode 2 and mode 3 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor IN an intel 8085A microprocessor, why is READY signal used? To indicate to user that the microprocessor is working and is ready for use. To provide proper WAIT states when the microprocessor is communicating with a slow peripheral device. None of these To slow down a fast peripheral device so as to communicate at the microprocessor’s device. To indicate to user that the microprocessor is working and is ready for use. To provide proper WAIT states when the microprocessor is communicating with a slow peripheral device. None of these To slow down a fast peripheral device so as to communicate at the microprocessor’s device. ANSWER DOWNLOAD EXAMIANS APP
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