Microprocessor Which one of the following interrupt/interrupts is/are only level triggering? RST 6.5 both ‘a’ and ‘b’ RST 5.5 TRAP RST 6.5 both ‘a’ and ‘b’ RST 5.5 TRAP ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following conditions is not allowed in an RS latch? R is asserted, S is negated R is negated, S is negated R is negated, S is asserted R is asserted, S is asserted R is asserted, S is negated R is negated, S is negated R is negated, S is asserted R is asserted, S is asserted ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which language could be used for programming an FPGA. VHDL Verilog None Both A and B VHDL Verilog None Both A and B ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Inintel 8085A microprocessor ALE signal is made high to To disable data bus Enable the data bus to be used as low order address bus To latch data D0-D7 from data bus To achieve all the functions listed above To disable data bus Enable the data bus to be used as low order address bus To latch data D0-D7 from data bus To achieve all the functions listed above ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The microprocessor issues ALE during first T-state of fetch cycle only memory WRITE cycle only every machine cycle memory READ cycle only fetch cycle only memory WRITE cycle only every machine cycle memory READ cycle only ANSWER DOWNLOAD EXAMIANS APP
EXAMIANS