Microprocessor Which one of the following interrupt/interrupts is/are only level triggering? RST 6.5 TRAP RST 5.5 both ‘a’ and ‘b’ RST 6.5 TRAP RST 5.5 both ‘a’ and ‘b’ ANSWER DOWNLOAD EXAMIANS APP
Microprocessor IN an intel 8085A microprocessor, why is READY signal used? To slow down a fast peripheral device so as to communicate at the microprocessor’s device. To indicate to user that the microprocessor is working and is ready for use. To provide proper WAIT states when the microprocessor is communicating with a slow peripheral device. None of these To slow down a fast peripheral device so as to communicate at the microprocessor’s device. To indicate to user that the microprocessor is working and is ready for use. To provide proper WAIT states when the microprocessor is communicating with a slow peripheral device. None of these ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 P flag is reset when the result has odd parity P flag is set when the result has even parity P flag is set when the result has odd parity P flag is reset when the result has even parity P flag is reset when the result has odd parity P flag is set when the result has even parity P flag is set when the result has odd parity P flag is reset when the result has even parity ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Segment override prefix (SOP) is used when a default offset register is not used with its default base segment register but with a different base register. Reason(R): The offset registers IP and SP can never be associated with any other segment registers apart from their respective default segments. Both A & R are true and R is the correct explanation of A. Both A & R are true but R is not the correct explanation of A. A is true but R is false. A is false but R is true. Both A & R are true and R is the correct explanation of A. Both A & R are true but R is not the correct explanation of A. A is true but R is false. A is false but R is true. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 microprocessor, in response to RST 7.5 interrupts the execution is transferred to memory location 0034H 003CH 002CH 0000H 0034H 003CH 002CH 0000H ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 microprocessor which one of the following statement is wrong serial I/O is not possible there is a pin available for serial input serial I/O is possible through SIM and RIM instruction there is a pin available for serial output serial I/O is not possible there is a pin available for serial input serial I/O is possible through SIM and RIM instruction there is a pin available for serial output ANSWER DOWNLOAD EXAMIANS APP
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