Microprocessor Which one of the following interrupt/interrupts is/are only level triggering? TRAP RST 5.5 both ‘a’ and ‘b’ RST 6.5 TRAP RST 5.5 both ‘a’ and ‘b’ RST 6.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which one of the following statement is false? A microprocessor has an ALU A microprocessor has bi-directional data bus A microprocessor has unidirectional address bus A microprocessor has bi-directional address bus A microprocessor has an ALU A microprocessor has bi-directional data bus A microprocessor has unidirectional address bus A microprocessor has bi-directional address bus ANSWER DOWNLOAD EXAMIANS APP
Microprocessor SPHL instruction copies the content of H-L register pair to the _________. B-C D-E Stack Pointer PSW B-C D-E Stack Pointer PSW ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The data bus of any microprocessor is always Either unidirectional or bi-directional Unidirectional None Bi-directional Either unidirectional or bi-directional Unidirectional None Bi-directional ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The output data lines of microprocessor and memories are usually tristated because More than one device can transmit over the data bus at the same time The data line can be multiplexed for both input and output More than one device can transmit information over the data bus by enabling only one device at a time It increases the speed of data transfer over the data bus More than one device can transmit over the data bus at the same time The data line can be multiplexed for both input and output More than one device can transmit information over the data bus by enabling only one device at a time It increases the speed of data transfer over the data bus ANSWER DOWNLOAD EXAMIANS APP
Microprocessor When the write enable input is not asserted, the gated D latch _________ its output. Complements Clears Can not change Sets Complements Clears Can not change Sets ANSWER DOWNLOAD EXAMIANS APP
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