Microprocessor The output data lines of microprocessor and memories are usually tristated because The data line can be multiplexed for both input and output More than one device can transmit over the data bus at the same time It increases the speed of data transfer over the data bus More than one device can transmit information over the data bus by enabling only one device at a time The data line can be multiplexed for both input and output More than one device can transmit over the data bus at the same time It increases the speed of data transfer over the data bus More than one device can transmit information over the data bus by enabling only one device at a time ANSWER DOWNLOAD EXAMIANS APP
Microprocessor How many machine cycles are required for execution of IN 30H instruction 6 3 4 5 6 3 4 5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Ready signal of microprocessor is used to detect whether a peripheral is ready for the data transfer or not. Reason(R): In the microprocessor during data transfer operations, the wait states are added by forcing the ready signal low. A is true but R is false. Both A & R are true and R is the correct explanation of A. Both A & R are true but R is not the correct explanation of A . A is false but R is true. A is true but R is false. Both A & R are true and R is the correct explanation of A. Both A & R are true but R is not the correct explanation of A . A is false but R is true. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In microprocessor based system DMA refers to None of these direct memory access for the I/O device direct memory access for the user direct memory access for microprocessor None of these direct memory access for the I/O device direct memory access for the user direct memory access for microprocessor ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In one’s complement 8 bit representation 11111111 represents -1 -0 +0 1 -1 -0 +0 1 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor At the beginning of a fetch cycle, the contents of the program counter are transferred to address bus. incremented by one. transferred to memory data register. transferred to memory address register . transferred to address bus. incremented by one. transferred to memory data register. transferred to memory address register . ANSWER DOWNLOAD EXAMIANS APP
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