Microprocessor The output data lines of microprocessor and memories are usually tristated because The data line can be multiplexed for both input and output More than one device can transmit over the data bus at the same time It increases the speed of data transfer over the data bus More than one device can transmit information over the data bus by enabling only one device at a time The data line can be multiplexed for both input and output More than one device can transmit over the data bus at the same time It increases the speed of data transfer over the data bus More than one device can transmit information over the data bus by enabling only one device at a time ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. None of these Both ‘b’ and ‘c’ Execution Unit (EU) Bus Interface Unit (BIU) None of these Both ‘b’ and ‘c’ Execution Unit (EU) Bus Interface Unit (BIU) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which one of the following instruction may be used to clear the accumulator content irrespective of its initial value? SUB A CLR A MOV A, 00H ORA A SUB A CLR A MOV A, 00H ORA A ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following conditions is not allowed in an RS latch? R is negated, S is negated R is asserted, S is asserted R is negated, S is asserted R is asserted, S is negated R is negated, S is negated R is asserted, S is asserted R is negated, S is asserted R is asserted, S is negated ANSWER DOWNLOAD EXAMIANS APP
Microprocessor RST 3 instruction will cause the processor to branch to the location 0000H 0024H 0028H 0018H 0000H 0024H 0028H 0018H ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which one of the following microprocessor has 16-bit data bus? 6502 8085 68000 Z-80 6502 8085 68000 Z-80 ANSWER DOWNLOAD EXAMIANS APP
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