Microprocessor The output data lines of microprocessor and memories are usually tristated because The data line can be multiplexed for both input and output It increases the speed of data transfer over the data bus More than one device can transmit information over the data bus by enabling only one device at a time More than one device can transmit over the data bus at the same time The data line can be multiplexed for both input and output It increases the speed of data transfer over the data bus More than one device can transmit information over the data bus by enabling only one device at a time More than one device can transmit over the data bus at the same time ANSWER DOWNLOAD EXAMIANS APP
Microprocessor While STC instruction executes, no flags will be affected. only carry and zero flags will be affected. all flags will be affected. only carry flag will be affected. no flags will be affected. only carry and zero flags will be affected. all flags will be affected. only carry flag will be affected. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor After RESET 8255 will be in mode 0; all ports are input mode 2 unchanged condition mode 0; all ports are output mode 0; all ports are input mode 2 unchanged condition mode 0; all ports are output ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Identify the programmable interval timer from the following 8275 8252 8253 8279 8275 8252 8253 8279 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Identify the non-programmable interfacing device from the following 8255. 8295. 8212. 8257. 8255. 8295. 8212. 8257. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor ‘Burst refresh’ in DRAM is also called Distributed refresh Hidden refresh Concentrated refresh None of these Distributed refresh Hidden refresh Concentrated refresh None of these ANSWER DOWNLOAD EXAMIANS APP
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