Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. Both ‘b’ and ‘c’ Execution Unit (EU) None of these Bus Interface Unit (BIU) Both ‘b’ and ‘c’ Execution Unit (EU) None of these Bus Interface Unit (BIU) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following instruction will never affect the zero flag? XRA R DCX Rp ORA R DCR R XRA R DCX Rp ORA R DCR R ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following pair of gates can form a latch? A pair of cross coupled NAND A pair of cross coupled OR A pair of cross copled AND A cross coupled NAND/OR A pair of cross coupled NAND A pair of cross coupled OR A pair of cross copled AND A cross coupled NAND/OR ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Because we wish to allow each ASCII code to occupy one location in memory, most memories are __________ addressable. DOUBLEWORD (32 bits) NIBBLE BYTE WORD (16 bits) DOUBLEWORD (32 bits) NIBBLE BYTE WORD (16 bits) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A microcomputer consists of memory a microprocessor I/O device All of these memory a microprocessor I/O device All of these ANSWER DOWNLOAD EXAMIANS APP
EXAMIANS