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Microprocessor

Microprocessor
IC 7485 cannot be cascadeD.

True
False

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Microprocessor
In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture.

 Both ‘b’ and ‘c’
 Execution Unit (EU)
 None of these
 Bus Interface Unit (BIU)

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Microprocessor
Which of the following instruction will never affect the zero flag?

 XRA R
 DCX Rp
 ORA R
 DCR R

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Microprocessor
Which of the following pair of gates can form a latch?

A pair of cross coupled NAND
A pair of cross coupled OR
A pair of cross copled AND
A cross coupled NAND/OR

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Microprocessor
Because we wish to allow each ASCII code to occupy one location in memory, most memories are __________ addressable.

DOUBLEWORD (32 bits)
NIBBLE
BYTE
WORD (16 bits)

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Microprocessor
A microcomputer consists of

 memory
 a microprocessor
 I/O device
All of these

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