Microprocessor Both the ALU and control section of CPU employ which special purpose storage location? Registers Decoders Accumulators Buffers Registers Decoders Accumulators Buffers ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The timing difference between a slow memory and fast processor can be resolved if Either A or B Processor is capable of waiting Neither A nor B External buffer is used Either A or B Processor is capable of waiting Neither A nor B External buffer is used ANSWER DOWNLOAD EXAMIANS APP
Microprocessor While STC instruction executes, no flags will be affected. only carry flag will be affected. only carry and zero flags will be affected. all flags will be affected. no flags will be affected. only carry flag will be affected. only carry and zero flags will be affected. all flags will be affected. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. Both ‘b’ and ‘c’ Execution Unit (EU) None of these Bus Interface Unit (BIU) Both ‘b’ and ‘c’ Execution Unit (EU) None of these Bus Interface Unit (BIU) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Because we wish to allow each ASCII code to occupy one location in memory, most memories are __________ addressable. WORD (16 bits) NIBBLE DOUBLEWORD (32 bits) BYTE WORD (16 bits) NIBBLE DOUBLEWORD (32 bits) BYTE ANSWER DOWNLOAD EXAMIANS APP
Microprocessor When any data transfer instruction, to transfer the data from memory to microprocessor, is executed the condition flags are not affected always reset affected indicating specific conditions always set not affected always reset affected indicating specific conditions always set ANSWER DOWNLOAD EXAMIANS APP
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