Microprocessor A combinational PLD with a programmable AND array and a fixed OR array is called a PROM PLD PAL PLA PROM PLD PAL PLA ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The content of the A15-A8 (higher order address lines) while executing “IN 8-bit port address” instruction are all bits reset (i.e. 00H) all bits set (i.e. FFH) irrelevant same as the content of A7-A0 all bits reset (i.e. 00H) all bits set (i.e. FFH) irrelevant same as the content of A7-A0 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Register pair used to indicate memory D and E H and L W and Z B and C D and E H and L W and Z B and C ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. None of these Both ‘b’ and ‘c’ Execution Unit (EU) Bus Interface Unit (BIU) None of these Both ‘b’ and ‘c’ Execution Unit (EU) Bus Interface Unit (BIU) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor DS directive in 8085 Forces the assembler to reserve one byte of memory Forces the assembler to reserve a specified number of consecutive bytes in the memory None of these Forces the assembler to reserve a specified number of bytes in the memory Forces the assembler to reserve one byte of memory Forces the assembler to reserve a specified number of consecutive bytes in the memory None of these Forces the assembler to reserve a specified number of bytes in the memory ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following conditions is not allowed in an RS latch? R is negated, S is asserted R is asserted, S is negated R is asserted, S is asserted R is negated, S is negated R is negated, S is asserted R is asserted, S is negated R is asserted, S is asserted R is negated, S is negated ANSWER DOWNLOAD EXAMIANS APP
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