Microprocessor A combinational PLD with a programmable AND array and a fixed OR array is called a PROM PAL PLD PLA PROM PAL PLD PLA ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following is not true during the execution of an interrupt service routine, which does not contain any EI instructions all interrupts except non-maskable interrupt are disabled the microprocessor cannot be interrupted by any mask able interrupt the microprocessor cannot be interrupted by any interrupt the microprocessor can be interrupted by a non-mask able interrupt all interrupts except non-maskable interrupt are disabled the microprocessor cannot be interrupted by any mask able interrupt the microprocessor cannot be interrupted by any interrupt the microprocessor can be interrupted by a non-mask able interrupt ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Temporary registers in 8085 are H and L. D and E. B and C. W and Z. H and L. D and E. B and C. W and Z. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The register which holds the information about the nature of results of arithmetic and logic operations is called as Flag register Process status register Accumulator Condition code register Flag register Process status register Accumulator Condition code register ANSWER DOWNLOAD EXAMIANS APP
Microprocessor FPGA means Forward Programmable Gate Array Forward Parallel Gate Array Field Programmable Gate Array Field Parallel Gate Array Forward Programmable Gate Array Forward Parallel Gate Array Field Programmable Gate Array Field Parallel Gate Array ANSWER DOWNLOAD EXAMIANS APP
Microprocessor HLDA signal in 8085 performs the following operation: Indicates that another master is requesting the use of the address and data buses. Indicates that the CPU has received the HOLD request and that it will relinquish the bus in the next clock cycle. Hold the data in the accumulator until the microprocessor is turned OFF. Indicates that the CPU has not received the HOLD request. Indicates that another master is requesting the use of the address and data buses. Indicates that the CPU has received the HOLD request and that it will relinquish the bus in the next clock cycle. Hold the data in the accumulator until the microprocessor is turned OFF. Indicates that the CPU has not received the HOLD request. ANSWER DOWNLOAD EXAMIANS APP
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