Microprocessor A combinational PLD with a programmable AND array and a fixed OR array is called a PLD PLA PAL PROM PLD PLA PAL PROM ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Address bus is unidirectional. Reason(R): Data bus is bidirectional A is true but R is false A is false but R is true Both A & R are true but R is not the correct explanation of A Both A & R are true and R is the correct explanation of A A is true but R is false A is false but R is true Both A & R are true but R is not the correct explanation of A Both A & R are true and R is the correct explanation of A ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. Bus Interface Unit (BIU) None of these Execution Unit (EU) Both ‘b’ and ‘c’ Bus Interface Unit (BIU) None of these Execution Unit (EU) Both ‘b’ and ‘c’ ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the data transfer is not possible in microprocessor memory to accumulator I/O device to accumulator memory to memory accumulator to memory memory to accumulator I/O device to accumulator memory to memory accumulator to memory ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The operations executed by two or more control units are referred as Micro-operations Bi control-operations Macro-operations Multi-operations Micro-operations Bi control-operations Macro-operations Multi-operations ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? T1 OP code fetch T2 OP code fetch T4 OP code fetch T3 OP code fetch T1 OP code fetch T2 OP code fetch T4 OP code fetch T3 OP code fetch ANSWER DOWNLOAD EXAMIANS APP
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