Microprocessor In an 8085 microprocessor based system, the contents of SP are 2000H. POP H instruction will transfer the contents of memory location 2000H and 1999H to H and L registers respectively 2000H and 1FFFH to H and L registers respectively 2001H and 2000H to H and L registers respectively 2001H and 2002H to H and L registers respectively 2000H and 1999H to H and L registers respectively 2000H and 1FFFH to H and L registers respectively 2001H and 2000H to H and L registers respectively 2001H and 2002H to H and L registers respectively ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Consider the following I) Sign flag II) Trap flag III) Parity flag IV) Auxiliary carry flag. Which one of the above flags is/are present in 8085 microprocessor? (I) ,(III) & (IV) (I) & (II) (II) & (III) (I) only (I) ,(III) & (IV) (I) & (II) (II) & (III) (I) only ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following interrupt is both level and edge sensitive? TRAP RST 7.5 INTR RST 5.5 TRAP RST 7.5 INTR RST 5.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The length of bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an indeterminate number of wait state clock cycles denoted by Tw. The wait states are always inserted between T2 & T3 T1 & T2 T4 & T1 T3 & T4 T2 & T3 T1 & T2 T4 & T1 T3 & T4 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Let the content of accumulator and register B be 0000 0100 and 0100 0000 respectively before execution of instruction SUB B. The content of accumulator after the execution of this instruction will be 11000100 00000100 01000000 010001000 11000100 00000100 01000000 010001000 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The microprocessor may be made to exit from HALT state by asserting READY line RESTART any of the five interrupt lines A or B or HOLD line READY line RESTART any of the five interrupt lines A or B or HOLD line ANSWER DOWNLOAD EXAMIANS APP
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