Microprocessor
The length of bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an indeterminate number of wait state clock cycles denoted by Tw. The wait states are always inserted between
Data transfer takes place between the I/O device and memory during every alternate clock cycle
DMA controller taking over the address, data and control buses while a block of data is transferred between memory and I/O device
The DMA control waiting for the microprocessor to finish execution of the program and then takes over the buses
While the microprocessor is executing a program an interface circuit takes over control of address, data, control buses when not in use by microprocessor
EXAMIANS