Microprocessor The length of bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an indeterminate number of wait state clock cycles denoted by Tw. The wait states are always inserted between T1 & T2 T2 & T3 T4 & T1 T3 & T4 T1 & T2 T2 & T3 T4 & T1 T3 & T4 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 microprocessor, in response to RST 7.5 interrupts the execution is transferred to memory location 003CH 0034H 002CH 0000H 003CH 0034H 002CH 0000H ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The number of hardware interrupts present in 8085 microprocessor are 8 16 5 10 8 16 5 10 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The data bus of any microprocessor is always Bi-directional None Unidirectional Either unidirectional or bi-directional Bi-directional None Unidirectional Either unidirectional or bi-directional ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The output data lines of microprocessor and memories are usually tristated because The data line can be multiplexed for both input and output More than one device can transmit information over the data bus by enabling only one device at a time It increases the speed of data transfer over the data bus More than one device can transmit over the data bus at the same time The data line can be multiplexed for both input and output More than one device can transmit information over the data bus by enabling only one device at a time It increases the speed of data transfer over the data bus More than one device can transmit over the data bus at the same time ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which language could be used for programming an FPGA. Verilog Both A and B VHDL None Verilog Both A and B VHDL None ANSWER DOWNLOAD EXAMIANS APP
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