Microprocessor Which of the following is not true during the execution of an interrupt service routine, which does not contain any EI instructions all interrupts except non-maskable interrupt are disabled the microprocessor can be interrupted by a non-mask able interrupt the microprocessor cannot be interrupted by any interrupt the microprocessor cannot be interrupted by any mask able interrupt all interrupts except non-maskable interrupt are disabled the microprocessor can be interrupted by a non-mask able interrupt the microprocessor cannot be interrupted by any interrupt the microprocessor cannot be interrupted by any mask able interrupt ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which memory has read operation, byte erase, byte write and chip erase? Both B and C RAM UVEPROM EEPROM Both B and C RAM UVEPROM EEPROM ANSWER DOWNLOAD EXAMIANS APP
Microprocessor What is mean by ALU Arithmetic logic unsigned Arithmetic logic unit Arithmetic local unsigned Arithmetic logic upgrade Arithmetic logic unsigned Arithmetic logic unit Arithmetic local unsigned Arithmetic logic upgrade ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? T1 OP code fetch T3 OP code fetch T2 OP code fetch T4 OP code fetch T1 OP code fetch T3 OP code fetch T2 OP code fetch T4 OP code fetch ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following interrupt is both level and edge sensitive? RST 5.5 INTR RST 7.5 TRAP RST 5.5 INTR RST 7.5 TRAP ANSWER DOWNLOAD EXAMIANS APP
Microprocessor RST 3 instruction will cause the processor to branch to the location 0000H 0024H 0028H 0018H 0000H 0024H 0028H 0018H ANSWER DOWNLOAD EXAMIANS APP
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