Microprocessor Using one 8259 IC is equivalent to providing …………. INTR pins on 8085 8 12 16 18 8 12 16 18 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Pick out the matching pair HOLD; DMA S0;S1;wait status READY; RIM SID; SIM HOLD; DMA S0;S1;wait status READY; RIM SID; SIM ANSWER DOWNLOAD EXAMIANS APP
Microprocessor DS directive in 8085 Forces the assembler to reserve a specified number of consecutive bytes in the memory None of these Forces the assembler to reserve one byte of memory Forces the assembler to reserve a specified number of bytes in the memory Forces the assembler to reserve a specified number of consecutive bytes in the memory None of these Forces the assembler to reserve one byte of memory Forces the assembler to reserve a specified number of bytes in the memory ANSWER DOWNLOAD EXAMIANS APP
Microprocessor When referring to instruction words, a mnemonic is a short abbreviation for the data word stored at the operand address. shorthand for machine language. a short abbreviation for the operation to be performed. a short abbreviation for the operand address. a short abbreviation for the data word stored at the operand address. shorthand for machine language. a short abbreviation for the operation to be performed. a short abbreviation for the operand address. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Segment override prefix (SOP) is used when a default offset register is not used with its default base segment register but with a different base register. Reason(R): The offset registers IP and SP can never be associated with any other segment registers apart from their respective default segments. Both A & R are true but R is not the correct explanation of A. A is false but R is true. Both A & R are true and R is the correct explanation of A. A is true but R is false. Both A & R are true but R is not the correct explanation of A. A is false but R is true. Both A & R are true and R is the correct explanation of A. A is true but R is false. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor An I/O processor controls the flow of information between Cache memory and I/O devices Cache and main memory Main memory and I/O devices Two I/O devices Cache memory and I/O devices Cache and main memory Main memory and I/O devices Two I/O devices ANSWER DOWNLOAD EXAMIANS APP
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