Microprocessor Assertion(A): Ready signal of microprocessor is used to detect whether a peripheral is ready for the data transfer or not. Reason(R): In the microprocessor during data transfer operations, the wait states are added by forcing the ready signal low. A is false but R is true. A is true but R is false. Both A & R are true but R is not the correct explanation of A . Both A & R are true and R is the correct explanation of A. A is false but R is true. A is true but R is false. Both A & R are true but R is not the correct explanation of A . Both A & R are true and R is the correct explanation of A. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? T3 OP code fetch T4 OP code fetch T2 OP code fetch T1 OP code fetch T3 OP code fetch T4 OP code fetch T2 OP code fetch T1 OP code fetch ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which one of the following ICs is used to interface keyboard and display? 8279 8259 8251 8253 8279 8259 8251 8253 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following is not true during the execution of an interrupt service routine, which does not contain any EI instructions the microprocessor can be interrupted by a non-mask able interrupt the microprocessor cannot be interrupted by any mask able interrupt the microprocessor cannot be interrupted by any interrupt all interrupts except non-maskable interrupt are disabled the microprocessor can be interrupted by a non-mask able interrupt the microprocessor cannot be interrupted by any mask able interrupt the microprocessor cannot be interrupted by any interrupt all interrupts except non-maskable interrupt are disabled ANSWER DOWNLOAD EXAMIANS APP
Microprocessor What is the size (in bytes) of Prefetch queue in 8086? 6. 3. 2. 4. 6. 3. 2. 4. ANSWER DOWNLOAD EXAMIANS APP
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