Microprocessor In 8085 P flag is set when the result has even parity P flag is set when the result has odd parity P flag is reset when the result has even parity P flag is reset when the result has odd parity P flag is set when the result has even parity P flag is set when the result has odd parity P flag is reset when the result has even parity P flag is reset when the result has odd parity ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which one of the following interrupt/interrupts is/are only level triggering? RST 6.5 TRAP RST 5.5 both ‘a’ and ‘b’ RST 6.5 TRAP RST 5.5 both ‘a’ and ‘b’ ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In microprocessor based system I/O ports are used to interface the I/P device only the O/P devices only the I/O devices and memory chips all the I/O devices the I/P device only the O/P devices only the I/O devices and memory chips all the I/O devices ANSWER DOWNLOAD EXAMIANS APP
Microprocessor While CMP B instruction executes, only carry flag will be affected. only carry and zero flags will be affected. all flags will be affected. no flags will be affected. only carry flag will be affected. only carry and zero flags will be affected. all flags will be affected. no flags will be affected. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following interrupt is both level and edge sensitive? TRAP RST 5.5 RST 7.5 INTR TRAP RST 5.5 RST 7.5 INTR ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A structure that stores a number of bits taken “together as a unit” is a Register Decoder Mux Gate Register Decoder Mux Gate ANSWER DOWNLOAD EXAMIANS APP
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