Microprocessor
In 8085

P flag is reset when the result has odd parity
P flag is set when the result has odd parity
P flag is reset when the result has even parity
P flag is set when the result has even parity

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Microprocessor
The output data lines of microprocessor and memories are usually tristated because

 The data line can be multiplexed for both input and output
 More than one device can transmit information over the data bus by enabling only one device at a time
 It increases the speed of data transfer over the data bus
 More than one device can transmit over the data bus at the same time

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Microprocessor
IN an intel 8085A microprocessor, why is READY signal used?

 To provide proper WAIT states when the microprocessor is communicating with a slow peripheral device.
None of these
 To slow down a fast peripheral device so as to communicate at the microprocessor’s device.
 To indicate to user that the microprocessor is working and is ready for use.

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Microprocessor
Cycle stealing mode of DMA operation involves

 The DMA control waiting for the microprocessor to finish execution of the program and then takes over the buses
 While the microprocessor is executing a program an interface circuit takes over control of address, data, control buses when not in use by microprocessor
 DMA controller taking over the address, data and control buses while a block of data is transferred between memory and I/O device
 Data transfer takes place between the I/O device and memory during every alternate clock cycle

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