Microprocessor For a memory with a 16-bit address space, the addressability is Cannot be determined 2^16 bits 8 bits 16 bits Cannot be determined 2^16 bits 8 bits 16 bits ANSWER DOWNLOAD EXAMIANS APP
Microprocessor XCHG instruction exchanges the content of H-L with ______ register pair. Stack Pointer B-C PSW D-E Stack Pointer B-C PSW D-E ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A sequence of two registers that multiplies the content of DE register pair by two and stores the result in HL register pair (in 8085 assembly language) is PCHL & DAD D XCHG & DAD B XTHL & DAD H XCHG & DAD H PCHL & DAD D XCHG & DAD B XTHL & DAD H XCHG & DAD H ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Inintel 8085A microprocessor ALE signal is made high to To disable data bus Enable the data bus to be used as low order address bus To latch data D0-D7 from data bus To achieve all the functions listed above To disable data bus Enable the data bus to be used as low order address bus To latch data D0-D7 from data bus To achieve all the functions listed above ANSWER DOWNLOAD EXAMIANS APP
Microprocessor An 8-bit microprocessor can have ………….. address lines. 8 cannot be predicted 16 32 8 cannot be predicted 16 32 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The cycle required to fetch and execute an instruction in a 8085 microprocessor is which one of the following? Clock cycle Machine cycle Memory cycle Instruction cycle Clock cycle Machine cycle Memory cycle Instruction cycle ANSWER DOWNLOAD EXAMIANS APP
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