Microprocessor In order to complement the lower nibble of accumulator one can use XRI 0FH ORI 0FH CMA ANI 0FH XRI 0FH ORI 0FH CMA ANI 0FH ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following instruction is not possible in 8085? POP B POP 30 H POP PSW POP D POP B POP 30 H POP PSW POP D ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The 8085 microprocessor enters into bus idle machine cycle whenever RST 7.5 is recognized None of these INTR interrupt is recognized DAD RP instruction is executed RST 7.5 is recognized None of these INTR interrupt is recognized DAD RP instruction is executed ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Because we wish to allow each ASCII code to occupy one location in memory, most memories are __________ addressable. BYTE NIBBLE WORD (16 bits) DOUBLEWORD (32 bits) BYTE NIBBLE WORD (16 bits) DOUBLEWORD (32 bits) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A microcomputer consists of I/O device memory All of these a microprocessor I/O device memory All of these a microprocessor ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The output data lines of microprocessor and memories are usually tristated because More than one device can transmit information over the data bus by enabling only one device at a time More than one device can transmit over the data bus at the same time The data line can be multiplexed for both input and output It increases the speed of data transfer over the data bus More than one device can transmit information over the data bus by enabling only one device at a time More than one device can transmit over the data bus at the same time The data line can be multiplexed for both input and output It increases the speed of data transfer over the data bus ANSWER DOWNLOAD EXAMIANS APP
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