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Microprocessor

Microprocessor
In order to complement the lower nibble of accumulator one can use

 ORI 0FH
 CMA
 ANI 0FH
 XRI 0FH

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Microprocessor
When any data transfer instruction, to transfer the data from memory to microprocessor, is executed the condition flags are

 always set
 not affected
 affected indicating specific conditions
 always reset

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Microprocessor
Length of the instruction POP D is

 1 byte
 2 byte
 3 byte
 4 byte

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Microprocessor
In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture.

 Execution Unit (EU)
 Bus Interface Unit (BIU)
 None of these
 Both ‘b’ and ‘c’

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Microprocessor
Assertion(A): Address bus is unidirectional. Reason(R): Data bus is bidirectional

 A is true but R is false
 Both A & R are true and R is the correct explanation of A
 Both A & R are true but R is not the correct explanation of A
 A is false but R is true

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Microprocessor
While INX B instruction execute,

 only carry and zero flags will be affected
 all flags will be affected
 no flags will be affected
 only carry flag will be affected

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