Microprocessor In order to complement the lower nibble of accumulator one can use XRI 0FH CMA ANI 0FH ORI 0FH XRI 0FH CMA ANI 0FH ORI 0FH ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The content of the A15-A8 (higher order address lines) while executing “IN 8-bit port address” instruction are irrelevant same as the content of A7-A0 all bits set (i.e. FFH) all bits reset (i.e. 00H) irrelevant same as the content of A7-A0 all bits set (i.e. FFH) all bits reset (i.e. 00H) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A bus connected between the CPU and main memory that permits transfer of information between main memory and the CPU is known as Memory bus Address bus Control bus DMA bus Memory bus Address bus Control bus DMA bus ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Let the content of accumulator and register B be 0000 0100 and 0100 0000 respectively before execution of instruction SUB B. The content of accumulator after the execution of this instruction will be 010001000 11000100 00000100 01000000 010001000 11000100 00000100 01000000 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In a microprocessor based system the stack is always in ROM EPROM microprocessor RAM ROM EPROM microprocessor RAM ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. Execution Unit (EU) Bus Interface Unit (BIU) Both ‘b’ and ‘c’ None of these Execution Unit (EU) Bus Interface Unit (BIU) Both ‘b’ and ‘c’ None of these ANSWER DOWNLOAD EXAMIANS APP
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