Microprocessor The data lines of 8085 microprocessor are multiplexed with None of these status lines higher order address lines lower order address lines None of these status lines higher order address lines lower order address lines ANSWER DOWNLOAD EXAMIANS APP
Microprocessor When the write enable input is not asserted, the gated D latch _________ its output. Complements Clears Can not change Sets Complements Clears Can not change Sets ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A 37 bit mantissa has an accuracy of 11 decimal places 10 decimal places 6 decimal places 8 decimal places 11 decimal places 10 decimal places 6 decimal places 8 decimal places ANSWER DOWNLOAD EXAMIANS APP
Microprocessor ‘Burst refresh’ in DRAM is also called Distributed refresh Concentrated refresh Hidden refresh None of these Distributed refresh Concentrated refresh Hidden refresh None of these ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The reason for the presence of ALE pin in 8085, but not in 6800 is that None 8085 has multiplexed bus, whereas 6800 does not have 8085 uses I/O mapped I/O, whereas 6800 uses memory mapped I/O 8085 has 5 interrupts lines, whereas 6800 has only two None 8085 has multiplexed bus, whereas 6800 does not have 8085 uses I/O mapped I/O, whereas 6800 uses memory mapped I/O 8085 has 5 interrupts lines, whereas 6800 has only two ANSWER DOWNLOAD EXAMIANS APP
Microprocessor SPHL instruction copies the content of H-L register pair to the _________. D-E B-C Stack Pointer PSW D-E B-C Stack Pointer PSW ANSWER DOWNLOAD EXAMIANS APP
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