Microprocessor Which memory has read operation, byte erase, byte write and chip erase? UVEPROM RAM Both B and C EEPROM UVEPROM RAM Both B and C EEPROM ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The addressing mode in instruction PUSH B is direct register register indirect immediate direct register register indirect immediate ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The first machine cycle of an instruction is always A memory read cycle A memory write cycle An I/O read cycle A fetch cycle A memory read cycle A memory write cycle An I/O read cycle A fetch cycle ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Segment override prefix (SOP) is used when a default offset register is not used with its default base segment register but with a different base register. Reason(R): The offset registers IP and SP can never be associated with any other segment registers apart from their respective default segments. Both A & R are true but R is not the correct explanation of A. A is true but R is false. Both A & R are true and R is the correct explanation of A. A is false but R is true. Both A & R are true but R is not the correct explanation of A. A is true but R is false. Both A & R are true and R is the correct explanation of A. A is false but R is true. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A mask programmed ROM is erasable and programmable erasable electrically programmed by the user programmed at the time of fabrication erasable and programmable erasable electrically programmed by the user programmed at the time of fabrication ANSWER DOWNLOAD EXAMIANS APP
Microprocessor While STC instruction executes, only carry flag will be affected. all flags will be affected. only carry and zero flags will be affected. no flags will be affected. only carry flag will be affected. all flags will be affected. only carry and zero flags will be affected. no flags will be affected. ANSWER DOWNLOAD EXAMIANS APP
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