Microprocessor A combinational PLD with a fixed AND array and a programmable OR array is called a PLD PLA PAL PROM PLD PLA PAL PROM ANSWER DOWNLOAD EXAMIANS APP
Microprocessor While STC instruction executes, only carry and zero flags will be affected. all flags will be affected. only carry flag will be affected. no flags will be affected. only carry and zero flags will be affected. all flags will be affected. only carry flag will be affected. no flags will be affected. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor PSW stands for accumulator contents accumulator and flag register contents none flag byte accumulator contents accumulator and flag register contents none flag byte ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 microprocessor system with memory mapped I/O, which of the following is true? Devices are accessed using IN and OUT instructions Devices have 8-bit address line Arithmetic and logic operations can be directly performed with the I/O data There can be maximum of 256 input devices and 256 output devices Devices are accessed using IN and OUT instructions Devices have 8-bit address line Arithmetic and logic operations can be directly performed with the I/O data There can be maximum of 256 input devices and 256 output devices ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Ready signal of microprocessor is used to detect whether a peripheral is ready for the data transfer or not. Reason(R): In the microprocessor during data transfer operations, the wait states are added by forcing the ready signal low. Both A & R are true and R is the correct explanation of A. A is true but R is false. Both A & R are true but R is not the correct explanation of A . A is false but R is true. Both A & R are true and R is the correct explanation of A. A is true but R is false. Both A & R are true but R is not the correct explanation of A . A is false but R is true. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A sequence of two registers that multiplies the content of DE register pair by two and stores the result in HL register pair (in 8085 assembly language) is PCHL & DAD D XTHL & DAD H XCHG & DAD B XCHG & DAD H PCHL & DAD D XTHL & DAD H XCHG & DAD B XCHG & DAD H ANSWER DOWNLOAD EXAMIANS APP
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