Microprocessor A combinational PLD with a fixed AND array and a programmable OR array is called a PROM PAL PLA PLD PROM PAL PLA PLD ANSWER DOWNLOAD EXAMIANS APP
Microprocessor After RESET 8255 will be in mode 0; all ports are output mode 2 unchanged condition mode 0; all ports are input mode 0; all ports are output mode 2 unchanged condition mode 0; all ports are input ANSWER DOWNLOAD EXAMIANS APP
Microprocessor At the beginning of a fetch cycle, the contents of the program counter are incremented by one. transferred to memory address register . transferred to address bus. transferred to memory data register. incremented by one. transferred to memory address register . transferred to address bus. transferred to memory data register. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor When the write enable input is not asserted, the gated D latch _________ its output. Complements Clears Can not change Sets Complements Clears Can not change Sets ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During OPCODE fetch the state of S0 and S1 is 00 10 11 01 00 10 11 01 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A 37 bit mantissa has an accuracy of 8 decimal places 10 decimal places 11 decimal places 6 decimal places 8 decimal places 10 decimal places 11 decimal places 6 decimal places ANSWER DOWNLOAD EXAMIANS APP
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