Microprocessor In 8085 microprocessor, in response to RST 7.5 interrupts the execution is transferred to memory location 002CH 0000H 003CH 0034H 002CH 0000H 003CH 0034H ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A single instruction to clear the lower nibble of accumulator in 8085 language assembly is XRI FOH XRI 0FH ANI F0H ANI OFH XRI FOH XRI 0FH ANI F0H ANI OFH ANSWER DOWNLOAD EXAMIANS APP
Microprocessor What is the size (in bytes) of Prefetch queue in 8086? 2. 6. 4. 3. 2. 6. 4. 3. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Maximum number of I/O that can be addressed by the INTEL 8085 is 256 512 285 65536 256 512 285 65536 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 P flag is set when the result has odd parity P flag is reset when the result has even parity P flag is reset when the result has odd parity P flag is set when the result has even parity P flag is set when the result has odd parity P flag is reset when the result has even parity P flag is reset when the result has odd parity P flag is set when the result has even parity ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The addressing mode in instruction PUSH B is immediate direct register indirect register immediate direct register indirect register ANSWER DOWNLOAD EXAMIANS APP
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