Microprocessor The 8085 microprocessor enters into bus idle machine cycle whenever INTR interrupt is recognized DAD RP instruction is executed RST 7.5 is recognized None of these INTR interrupt is recognized DAD RP instruction is executed RST 7.5 is recognized None of these ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following instruction is not possible in 8085? POP D POP 30 H POP PSW POP B POP D POP 30 H POP PSW POP B ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The addressing mode in instruction PUSH B is immediate register indirect register direct immediate register indirect register direct ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Ready signal of microprocessor is used to detect whether a peripheral is ready for the data transfer or not. Reason(R): In the microprocessor during data transfer operations, the wait states are added by forcing the ready signal low. Both A & R are true but R is not the correct explanation of A . Both A & R are true and R is the correct explanation of A. A is true but R is false. A is false but R is true. Both A & R are true but R is not the correct explanation of A . Both A & R are true and R is the correct explanation of A. A is true but R is false. A is false but R is true. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A 37 bit mantissa has an accuracy of 6 decimal places 8 decimal places 10 decimal places 11 decimal places 6 decimal places 8 decimal places 10 decimal places 11 decimal places ANSWER DOWNLOAD EXAMIANS APP
Microprocessor PSW stands for flag byte accumulator and flag register contents accumulator contents none flag byte accumulator and flag register contents accumulator contents none ANSWER DOWNLOAD EXAMIANS APP
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