Microprocessor Which general register or general register pair is incremented/decremented by 2 during PUSH and POP instructions? H-L. Program Counter. D-E. Stack Pointer. H-L. Program Counter. D-E. Stack Pointer. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The character set of Fortran 77 includes lower case alphabets a to z. False True False True ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The correct sequence of steps in the instruction cycle of a basic computer is Fetch, Read effective address, Decode and Execute. Fetch, Decode, Read effective address and, Execute. Read effective address, Decode, Fetch and Execute. Fetch, Execute, Decode and Read effective address. Fetch, Read effective address, Decode and Execute. Fetch, Decode, Read effective address and, Execute. Read effective address, Decode, Fetch and Execute. Fetch, Execute, Decode and Read effective address. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor PSW stands for flag byte accumulator contents accumulator and flag register contents none flag byte accumulator contents accumulator and flag register contents none ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The relation among IC (Instruction Cycle), FC (Fetch cycle) and EC (Execute Cycle) is IC = FC - EC EC = IC + FC IC = FC + 2EC IC = FC + EC IC = FC - EC EC = IC + FC IC = FC + 2EC IC = FC + EC ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following conditions is not allowed in an RS latch? R is asserted, S is asserted R is negated, S is asserted R is asserted, S is negated R is negated, S is negated R is asserted, S is asserted R is negated, S is asserted R is asserted, S is negated R is negated, S is negated ANSWER DOWNLOAD EXAMIANS APP
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