Microprocessor Temporary registers in 8085 are D and E. W and Z. B and C. H and L. D and E. W and Z. B and C. H and L. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. None of these Bus Interface Unit (BIU) Execution Unit (EU) Both ‘b’ and ‘c’ None of these Bus Interface Unit (BIU) Execution Unit (EU) Both ‘b’ and ‘c’ ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which general register or general register pair is incremented/decremented by 2 during PUSH and POP instructions? Program Counter. D-E. Stack Pointer. H-L. Program Counter. D-E. Stack Pointer. H-L. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor PSW stands for accumulator contents flag byte accumulator and flag register contents none accumulator contents flag byte accumulator and flag register contents none ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assuming LSB is at position 0 and MSB at position 7, which bit positions are not used (Undefined) in flag register of an 8085 microprocessor? 1, 3, 4 1, 3, 5 1, 2, 5 2, 3, 5 1, 3, 4 1, 3, 5 1, 2, 5 2, 3, 5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In an intel 8085A, which is the first machine cycle of an instruction? A memory write cycle An op-code fetch cycle An I/O read cycle A memory read cycle A memory write cycle An op-code fetch cycle An I/O read cycle A memory read cycle ANSWER DOWNLOAD EXAMIANS APP
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