Microprocessor
Which of the following conditions is not allowed in an RS latch?

R is asserted, S is negated
R is negated, S is negated
R is negated, S is asserted
R is asserted, S is asserted

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Microprocessor
How can we make any bit of a register “1”?

 OR that bit with “1” and remaining bits with “0”.
 AND that bit with “0” and remaining bits with “1”.
 AND that bit with “1” and remaining bits with “0”.
 OR that bit with “0” and remaining bits with “1”.

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