Microprocessor When the write enable input is not asserted, the gated D latch _________ its output. Sets Complements Clears Can not change Sets Complements Clears Can not change ANSWER DOWNLOAD EXAMIANS APP
Microprocessor S0 and S1 pins are used for acknowledging the interrupt serial communication indicating the processor’s status None of these acknowledging the interrupt serial communication indicating the processor’s status None of these ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The first machine cycle of an instruction is always An I/O read cycle A memory write cycle A fetch cycle A memory read cycle An I/O read cycle A memory write cycle A fetch cycle A memory read cycle ANSWER DOWNLOAD EXAMIANS APP
Microprocessor CALL instruction is a ______ instruction. 1 bytes 3 bytes 4 bytes 2 bytes 1 bytes 3 bytes 4 bytes 2 bytes ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Consider the following I) Sign flag II) Trap flag III) Parity flag IV) Auxiliary carry flag. Which one of the above flags is/are present in 8085 microprocessor? (I) only (I) ,(III) & (IV) (I) & (II) (II) & (III) (I) only (I) ,(III) & (IV) (I) & (II) (II) & (III) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A microprocessor with a 12-bit address bus will be able to access 1 K bytes 4 K bytes 8 K bytes 10 K bytes 1 K bytes 4 K bytes 8 K bytes 10 K bytes ANSWER DOWNLOAD EXAMIANS APP
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