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Microprocessor

Microprocessor
When the write enable input is not asserted, the gated D latch _________ its output.

Clears
Sets
Complements
Can not change

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Microprocessor
The minimum number of transistors required to implement a two input AND gate is

2
8
4
6

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Microprocessor
If m is a power of 2, the number of select lines required for an m-input mux is:

2^m
log2 (m)
2*m
m

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Microprocessor
During the execution of the instruction, the ________tests the status and control flags and updates them based on the results of executing the instruction.

 Bus Interface Unit (BIU)
 Both ‘c’ and ‘d’
 None of these
 Execution Unit (EU)

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Microprocessor
Which one of the following circuits transmits two messages simultaneously in one direction

 Simplex
 Quadruplex
 Diplex
 Duplex

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Microprocessor
The operating modes of 8255 A are called

Mode 0 and mode 2
Mode 0, mode 1 and mode 2
Mode 0, mode 2 and mode 3
Mode 0 and mode 1

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