Microprocessor When the write enable input is not asserted, the gated D latch _________ its output. Can not change Clears Complements Sets Can not change Clears Complements Sets ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The first machine cycle of an instruction is always An I/O read cycle A memory write cycle A memory read cycle A fetch cycle An I/O read cycle A memory write cycle A memory read cycle A fetch cycle ANSWER DOWNLOAD EXAMIANS APP
Microprocessor When .9432 E – 4 is subtracted from .5452 E – 3 in normalized floating point mode None of the numbers is changed .5452 E – 3 is changed to 5.452 E – 4 but .9432 E – 4 is not changed Both Ihe numbers are changed and their exponents are, made equal to -5 .9432 E – 4 is changed to .09432 E – 3 and .5452 E – 3 is not changed None of the numbers is changed .5452 E – 3 is changed to 5.452 E – 4 but .9432 E – 4 is not changed Both Ihe numbers are changed and their exponents are, made equal to -5 .9432 E – 4 is changed to .09432 E – 3 and .5452 E – 3 is not changed ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Total number of modes the 8253 can work 8 6 4 12 8 6 4 12 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Identify the programmable DMA controller from the following 8253 8279 8257 8251 8253 8279 8257 8251 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The operations executed by two or more control units are referred as Macro-operations Bi control-operations Multi-operations Micro-operations Macro-operations Bi control-operations Multi-operations Micro-operations ANSWER DOWNLOAD EXAMIANS APP
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