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Microprocessor

Microprocessor
When the write enable input is not asserted, the gated D latch _________ its output.

Clears
Complements
Can not change
Sets

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Microprocessor
The stack is nothing but a set of

 reserved RAM address space
 reserved I/O address space
 reserved ROM address space
None of these

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Microprocessor
Which one of the following interrupt/interrupts is/are only level triggering?

 TRAP
 RST 6.5
 both ‘a’ and ‘b’
 RST 5.5

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Microprocessor
Which one of the following statement is false?

 A microprocessor has bi-directional address bus
 A microprocessor has bi-directional data bus
 A microprocessor has unidirectional address bus
 A microprocessor has an ALU

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Microprocessor
Let the content of accumulator and register B be 0000 0100 and 0100 0000 respectively before execution of instruction SUB B. The content of accumulator after the execution of this instruction will be

 00000100
 11000100
 01000000
 010001000

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Microprocessor
The ROM programmed during manufacturing process itself is called

 EEPROM
 MROM
 PROM
 EPROM

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