Microprocessor When the write enable input is not asserted, the gated D latch _________ its output. Clears Can not change Complements Sets Clears Can not change Complements Sets ANSWER DOWNLOAD EXAMIANS APP
Microprocessor At the beginning of a fetch cycle, the contents of the program counter are incremented by one. transferred to memory data register. transferred to memory address register . transferred to address bus. incremented by one. transferred to memory data register. transferred to memory address register . transferred to address bus. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following interrupt is both level and edge sensitive? TRAP INTR RST 5.5 RST 7.5 TRAP INTR RST 5.5 RST 7.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During the execution of the instruction, the ________tests the status and control flags and updates them based on the results of executing the instruction. Execution Unit (EU) None of these Both ‘c’ and ‘d’ Bus Interface Unit (BIU) Execution Unit (EU) None of these Both ‘c’ and ‘d’ Bus Interface Unit (BIU) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The frequency of the driving network connected between pins 1 and 2 of 8085 microprocessor is four times the desired frequency twice the desired frequency equal to the desired frequency None of these four times the desired frequency twice the desired frequency equal to the desired frequency None of these ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following conditions is not allowed in an RS latch? R is asserted, S is negated R is negated, S is negated R is asserted, S is asserted R is negated, S is asserted R is asserted, S is negated R is negated, S is negated R is asserted, S is asserted R is negated, S is asserted ANSWER DOWNLOAD EXAMIANS APP
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