Microprocessor When the write enable input is not asserted, the gated D latch _________ its output. Complements Sets Can not change Clears Complements Sets Can not change Clears ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A bus connected between the CPU and main memory that permits transfer of information between main memory and the CPU is known as DMA bus Control bus Memory bus Address bus DMA bus Control bus Memory bus Address bus ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The operating modes of 8255 A are called Mode 0 and mode 1 Mode 0, mode 2 and mode 3 Mode 0, mode 1 and mode 2 Mode 0 and mode 2 Mode 0 and mode 1 Mode 0, mode 2 and mode 3 Mode 0, mode 1 and mode 2 Mode 0 and mode 2 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor If the sign bit of mantissa is 0 and the exponent is increased from a positive to a more negative number the result is A larger floating point number A smaller floating point number A negative floating point number Either A or B depending on the actual number A larger floating point number A smaller floating point number A negative floating point number Either A or B depending on the actual number ANSWER DOWNLOAD EXAMIANS APP
Microprocessor ‘Burst refresh’ in DRAM is also called Hidden refresh None of these Concentrated refresh Distributed refresh Hidden refresh None of these Concentrated refresh Distributed refresh ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 microprocessor system with memory mapped I/O, which of the following is true? Devices have 8-bit address line Devices are accessed using IN and OUT instructions There can be maximum of 256 input devices and 256 output devices Arithmetic and logic operations can be directly performed with the I/O data Devices have 8-bit address line Devices are accessed using IN and OUT instructions There can be maximum of 256 input devices and 256 output devices Arithmetic and logic operations can be directly performed with the I/O data ANSWER DOWNLOAD EXAMIANS APP
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