Microprocessor XCHG instruction exchanges the content of H-L with ______ register pair. B-C PSW D-E Stack Pointer B-C PSW D-E Stack Pointer ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In order to complement the lower nibble of accumulator one can use ANI 0FH CMA ORI 0FH XRI 0FH ANI 0FH CMA ORI 0FH XRI 0FH ANSWER DOWNLOAD EXAMIANS APP
Microprocessor When .9432 E – 4 is subtracted from .5452 E – 3 in normalized floating point mode None of the numbers is changed Both Ihe numbers are changed and their exponents are, made equal to -5 .5452 E – 3 is changed to 5.452 E – 4 but .9432 E – 4 is not changed .9432 E – 4 is changed to .09432 E – 3 and .5452 E – 3 is not changed None of the numbers is changed Both Ihe numbers are changed and their exponents are, made equal to -5 .5452 E – 3 is changed to 5.452 E – 4 but .9432 E – 4 is not changed .9432 E – 4 is changed to .09432 E – 3 and .5452 E – 3 is not changed ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The multiplexing of address bus and data buses is used in depends on the internal architecture. none of these. all the microprocessors. never multiplexed. depends on the internal architecture. none of these. all the microprocessors. never multiplexed. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor How can we make any bit of a register “0”? AND that bit with “0” and remaining bits with “1”. AND that bit with “1” and remaining bits with “0”. OR that bit with “1” and remaining bits with “0”. OR that bit with “0” and remaining bits with “1”. AND that bit with “0” and remaining bits with “1”. AND that bit with “1” and remaining bits with “0”. OR that bit with “1” and remaining bits with “0”. OR that bit with “0” and remaining bits with “1”. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The 8085 microprocessor enters into bus idle machine cycle whenever INTR interrupt is recognized RST 7.5 is recognized DAD RP instruction is executed None of these INTR interrupt is recognized RST 7.5 is recognized DAD RP instruction is executed None of these ANSWER DOWNLOAD EXAMIANS APP
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