Microprocessor XCHG instruction exchanges the content of H-L with ______ register pair. D-E Stack Pointer B-C PSW D-E Stack Pointer B-C PSW ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During OPCODE fetch the state of S0 and S1 is 00 10 11 01 00 10 11 01 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following interrupt is both level and edge sensitive? TRAP RST 7.5 INTR RST 5.5 TRAP RST 7.5 INTR RST 5.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Output of the assembler in machine codes is referred to as Object program Macroinstruction Source program Symbolic addressing Object program Macroinstruction Source program Symbolic addressing ANSWER DOWNLOAD EXAMIANS APP
Microprocessor RST 3 instruction will cause the processor to branch to the location 0024H 0000H 0028H 0018H 0024H 0000H 0028H 0018H ANSWER DOWNLOAD EXAMIANS APP
Microprocessor We say that a set of gates is logically complete if we can build any circuit without using any other kind of gates. Which of the following sets are logically complete Set of {AND,OR} Set of {EXOR, NOT} None of these Set of {AND,OR,NOT} Set of {AND,OR} Set of {EXOR, NOT} None of these Set of {AND,OR,NOT} ANSWER DOWNLOAD EXAMIANS APP
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