Microprocessor XCHG instruction exchanges the content of H-L with ______ register pair. Stack Pointer PSW B-C D-E Stack Pointer PSW B-C D-E ANSWER DOWNLOAD EXAMIANS APP
Microprocessor While STC instruction executes, all flags will be affected. no flags will be affected. only carry and zero flags will be affected. only carry flag will be affected. all flags will be affected. no flags will be affected. only carry and zero flags will be affected. only carry flag will be affected. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion (A): Each memory chip has its own address latch. Reason (R): ALE signal comes out of microprocessor 8085 and goes to memory chip. Both A and R are correct but R is not correct explanation of A A is correct R is wrong Both A and R are correct and R is correct explanation of A A is wrong R is correct Both A and R are correct but R is not correct explanation of A A is correct R is wrong Both A and R are correct and R is correct explanation of A A is wrong R is correct ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The addressing mode in instruction PUSH B is direct immediate register indirect register direct immediate register indirect register ANSWER DOWNLOAD EXAMIANS APP
Microprocessor At the beginning of a fetch cycle, the contents of the program counter are transferred to address bus. transferred to memory data register. transferred to memory address register . incremented by one. transferred to address bus. transferred to memory data register. transferred to memory address register . incremented by one. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Because we wish to allow each ASCII code to occupy one location in memory, most memories are __________ addressable. WORD (16 bits) DOUBLEWORD (32 bits) NIBBLE BYTE WORD (16 bits) DOUBLEWORD (32 bits) NIBBLE BYTE ANSWER DOWNLOAD EXAMIANS APP
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