The relation among IC (Instruction Cycle), FC (Fetch cycle) and EC (Execute Cycle) is

Microprocessor
The relation among IC (Instruction Cycle), FC (Fetch cycle) and EC (Execute Cycle) is

IC = FC + EC

IC = FC - EC

EC = IC + FC

IC = FC + 2EC

IC = FC + EC

IC = FC - EC

EC = IC + FC

IC = FC + 2EC

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Microprocessor
ALU (Arithmetic and Logic Unit ) of 8085 microprocessor consists of

Accumulator, temporary register, arithmetic, logic circuits and five flags

Accumulator, arithmetic and logic circuits

Accumulator, arithmetic, logic circuits and five flags

Accumulator, temporary register, arithmetic and logic circuits

Accumulator, temporary register, arithmetic, logic circuits and five flags

Accumulator, arithmetic and logic circuits

Accumulator, arithmetic, logic circuits and five flags

Accumulator, temporary register, arithmetic and logic circuits

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Microprocessor
Each instruction in an assembly language program has the following fields 1. Label field 2. Mnemonic field 3. Operand field 4. Comment field What are the correct sequence of these fields?

1, 3, 2 and 4

1, 2, 3 and 4

2, 4, 1 and 3

2, 1, 4 and 3

1, 3, 2 and 4

1, 2, 3 and 4

2, 4, 1 and 3

2, 1, 4 and 3

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Microprocessor
In 8085 microprocessor based system maximum possible number of input/output devices can be connected using I/O mapped I/O technique is

65536

256

512

64

65536

256

512

64

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Microprocessor
Cycle stealing mode of DMA operation involves

While the microprocessor is executing a program an interface circuit takes over control of address, data, control buses when not in use by microprocessor

The DMA control waiting for the microprocessor to finish execution of the program and then takes over the buses

DMA controller taking over the address, data and control buses while a block of data is transferred between memory and I/O device

Data transfer takes place between the I/O device and memory during every alternate clock cycle

While the microprocessor is executing a program an interface circuit takes over control of address, data, control buses when not in use by microprocessor

The DMA control waiting for the microprocessor to finish execution of the program and then takes over the buses

DMA controller taking over the address, data and control buses while a block of data is transferred between memory and I/O device

Data transfer takes place between the I/O device and memory during every alternate clock cycle

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Microprocessor
A bus connected between the CPU and main memory that permits transfer of information between main memory and the CPU is known as

Control bus

DMA bus

Memory bus

Address bus

Control bus

DMA bus

Memory bus

Address bus

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Microprocessor

Microprocessor The relation among IC (Instruction Cycle), FC (Fetch cycle) and EC (Execute Cycle) is

Microprocessor ALU (Arithmetic and Logic Unit ) of 8085 microprocessor consists of

Microprocessor Each instruction in an assembly language program has the following fields 1. Label field 2. Mnemonic field 3. Operand field 4. Comment field What are the correct sequence of these fields?

Microprocessor In 8085 microprocessor based system maximum possible number of input/output devices can be connected using I/O mapped I/O technique is

Microprocessor Cycle stealing mode of DMA operation involves

Microprocessor A bus connected between the CPU and main memory that permits transfer of information between main memory and the CPU is known as

Microprocessor
The relation among IC (Instruction Cycle), FC (Fetch cycle) and EC (Execute Cycle) is

Microprocessor
ALU (Arithmetic and Logic Unit ) of 8085 microprocessor consists of

Microprocessor
Each instruction in an assembly language program has the following fields 1. Label field 2. Mnemonic field 3. Operand field 4. Comment field What are the correct sequence of these fields?

Microprocessor
In 8085 microprocessor based system maximum possible number of input/output devices can be connected using I/O mapped I/O technique is

Microprocessor
Cycle stealing mode of DMA operation involves

Microprocessor
A bus connected between the CPU and main memory that permits transfer of information between main memory and the CPU is known as