Microprocessor The first machine cycle of an instruction is always A fetch cycle A memory write cycle An I/O read cycle A memory read cycle A fetch cycle A memory write cycle An I/O read cycle A memory read cycle ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which one of the following microprocessor has 16-bit data bus? 68000 8085 6502 Z-80 68000 8085 6502 Z-80 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Segment override prefix (SOP) is used when a default offset register is not used with its default base segment register but with a different base register. Reason(R): The offset registers IP and SP can never be associated with any other segment registers apart from their respective default segments. A is false but R is true. Both A & R are true but R is not the correct explanation of A. Both A & R are true and R is the correct explanation of A. A is true but R is false. A is false but R is true. Both A & R are true but R is not the correct explanation of A. Both A & R are true and R is the correct explanation of A. A is true but R is false. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The relation among IC (Instruction Cycle), FC (Fetch cycle) and EC (Execute Cycle) is EC = IC + FC IC = FC - EC IC = FC + 2EC IC = FC + EC EC = IC + FC IC = FC - EC IC = FC + 2EC IC = FC + EC ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The length of bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an indeterminate number of wait state clock cycles denoted by Tw. The wait states are always inserted between T3 & T4 T1 & T2 T4 & T1 T2 & T3 T3 & T4 T1 & T2 T4 & T1 T2 & T3 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which one of the following ICs is used to interface keyboard and display? 8259 8253 8251 8279 8259 8253 8251 8279 ANSWER DOWNLOAD EXAMIANS APP
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