Microprocessor A bus connected between the CPU and main memory that permits transfer of information between main memory and the CPU is known as DMA bus Control bus Address bus Memory bus DMA bus Control bus Address bus Memory bus ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The output data lines of microprocessor and memories are usually tristated because It increases the speed of data transfer over the data bus More than one device can transmit information over the data bus by enabling only one device at a time The data line can be multiplexed for both input and output More than one device can transmit over the data bus at the same time It increases the speed of data transfer over the data bus More than one device can transmit information over the data bus by enabling only one device at a time The data line can be multiplexed for both input and output More than one device can transmit over the data bus at the same time ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Maximum number of I/O that can be addressed by the INTEL 8085 is 512 65536 285 256 512 65536 285 256 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A microprocessor differentiates between op code, data/address at any time by its internal registers the program counter the sequence in which memory contents are fetched by it the stack pointer its internal registers the program counter the sequence in which memory contents are fetched by it the stack pointer ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Circuit A is a 1-bit adder; circuit B is a 1 bit multiplier.[Hint: Construct the truth table for the adder and the multiplier] None of these Circuit A has the same number of gates as circuit B Circuit B has more gates than circuit A Circuit A has more gates than circuit B None of these Circuit A has the same number of gates as circuit B Circuit B has more gates than circuit A Circuit A has more gates than circuit B ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The 8085 microprocessor enters into bus idle machine cycle whenever None of these RST 7.5 is recognized INTR interrupt is recognized DAD RP instruction is executed None of these RST 7.5 is recognized INTR interrupt is recognized DAD RP instruction is executed ANSWER DOWNLOAD EXAMIANS APP
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