Microprocessor After RESET 8255 will be in mode 0; all ports are input mode 2 unchanged condition mode 0; all ports are output mode 0; all ports are input mode 2 unchanged condition mode 0; all ports are output ANSWER DOWNLOAD EXAMIANS APP
Microprocessor While STC instruction executes, no flags will be affected. only carry and zero flags will be affected. only carry flag will be affected. all flags will be affected. no flags will be affected. only carry and zero flags will be affected. only carry flag will be affected. all flags will be affected. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor How many bytes in a zero memory page should be reserved for vectors used by RST instructions? 128. 32. 16. 64. 128. 32. 16. 64. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The operating modes of 8255 A are called Mode 0 and mode 2 Mode 0 and mode 1 Mode 0, mode 1 and mode 2 Mode 0, mode 2 and mode 3 Mode 0 and mode 2 Mode 0 and mode 1 Mode 0, mode 1 and mode 2 Mode 0, mode 2 and mode 3 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Segment override prefix (SOP) is used when a default offset register is not used with its default base segment register but with a different base register. Reason(R): The offset registers IP and SP can never be associated with any other segment registers apart from their respective default segments. A is true but R is false. A is false but R is true. Both A & R are true and R is the correct explanation of A. Both A & R are true but R is not the correct explanation of A. A is true but R is false. A is false but R is true. Both A & R are true and R is the correct explanation of A. Both A & R are true but R is not the correct explanation of A. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor An I/O processor controls the flow of information between Cache and main memory Two I/O devices Main memory and I/O devices Cache memory and I/O devices Cache and main memory Two I/O devices Main memory and I/O devices Cache memory and I/O devices ANSWER DOWNLOAD EXAMIANS APP
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