Microprocessor Register pair used to indicate memory H and L B and C W and Z D and E H and L B and C W and Z D and E ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The content of the A15-A8 (higher order address lines) while executing “IN 8-bit port address” instruction are all bits set (i.e. FFH) irrelevant all bits reset (i.e. 00H) same as the content of A7-A0 all bits set (i.e. FFH) irrelevant all bits reset (i.e. 00H) same as the content of A7-A0 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor SPHL instruction copies the content of H-L register pair to the _________. Stack Pointer PSW B-C D-E Stack Pointer PSW B-C D-E ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The interrupt facility is provided in microprocessor to change the sequence of the instructions being executed keep a control on the working of the microprocessor stop the microprocessor when desired stop the microprocessor when it starts malfunctioning change the sequence of the instructions being executed keep a control on the working of the microprocessor stop the microprocessor when desired stop the microprocessor when it starts malfunctioning ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In an intel 8085A, which is the first machine cycle of an instruction? An op-code fetch cycle An I/O read cycle A memory read cycle A memory write cycle An op-code fetch cycle An I/O read cycle A memory read cycle A memory write cycle ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 P flag is set when the result has even parity P flag is set when the result has odd parity P flag is reset when the result has odd parity P flag is reset when the result has even parity P flag is set when the result has even parity P flag is set when the result has odd parity P flag is reset when the result has odd parity P flag is reset when the result has even parity ANSWER DOWNLOAD EXAMIANS APP
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