Microprocessor A sequence of two registers that multiplies the content of DE register pair by two and stores the result in HL register pair (in 8085 assembly language) is XCHG & DAD B XCHG & DAD H XTHL & DAD H PCHL & DAD D XCHG & DAD B XCHG & DAD H XTHL & DAD H PCHL & DAD D ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Circuit A is a 1-bit adder; circuit B is a 1 bit multiplier.[Hint: Construct the truth table for the adder and the multiplier] Circuit A has more gates than circuit B None of these Circuit A has the same number of gates as circuit B Circuit B has more gates than circuit A Circuit A has more gates than circuit B None of these Circuit A has the same number of gates as circuit B Circuit B has more gates than circuit A ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following conditions is not allowed in an RS latch? R is negated, S is negated R is asserted, S is negated R is negated, S is asserted R is asserted, S is asserted R is negated, S is negated R is asserted, S is negated R is negated, S is asserted R is asserted, S is asserted ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which memory has read operation, byte erase, byte write and chip erase? RAM Both B and C UVEPROM EEPROM RAM Both B and C UVEPROM EEPROM ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The word size of 8085 microprocessor is 20-bit 4-bit 8-bit 16-bit 20-bit 4-bit 8-bit 16-bit ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. Bus Interface Unit (BIU) None of these Both ‘b’ and ‘c’ Execution Unit (EU) Bus Interface Unit (BIU) None of these Both ‘b’ and ‘c’ Execution Unit (EU) ANSWER DOWNLOAD EXAMIANS APP
EXAMIANS