Microprocessor An I/O processor controls the flow of information between Cache memory and I/O devices Cache and main memory Two I/O devices Main memory and I/O devices Cache memory and I/O devices Cache and main memory Two I/O devices Main memory and I/O devices ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Register pair used to indicate memory D and E W and Z B and C H and L D and E W and Z B and C H and L ANSWER DOWNLOAD EXAMIANS APP
Microprocessor CALL instruction is a ______ instruction. 2 bytes 3 bytes 1 bytes 4 bytes 2 bytes 3 bytes 1 bytes 4 bytes ANSWER DOWNLOAD EXAMIANS APP
Microprocessor During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)? T3 OP code fetch T1 OP code fetch T2 OP code fetch T4 OP code fetch T3 OP code fetch T1 OP code fetch T2 OP code fetch T4 OP code fetch ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. None of these Bus Interface Unit (BIU) Both ‘b’ and ‘c’ Execution Unit (EU) None of these Bus Interface Unit (BIU) Both ‘b’ and ‘c’ Execution Unit (EU) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The interrupt facility is provided in microprocessor to change the sequence of the instructions being executed keep a control on the working of the microprocessor stop the microprocessor when desired stop the microprocessor when it starts malfunctioning change the sequence of the instructions being executed keep a control on the working of the microprocessor stop the microprocessor when desired stop the microprocessor when it starts malfunctioning ANSWER DOWNLOAD EXAMIANS APP
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