Microprocessor An I/O processor controls the flow of information between Cache memory and I/O devices Cache and main memory Two I/O devices Main memory and I/O devices Cache memory and I/O devices Cache and main memory Two I/O devices Main memory and I/O devices ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which one of the following interrupt/interrupts is/are only level triggering? RST 5.5 RST 6.5 both ‘a’ and ‘b’ TRAP RST 5.5 RST 6.5 both ‘a’ and ‘b’ TRAP ANSWER DOWNLOAD EXAMIANS APP
Microprocessor When an 8085 microprocessor is reset, the address bus contains 0043H 003CH 0000H 002CH 0043H 003CH 0000H 002CH ANSWER DOWNLOAD EXAMIANS APP
Microprocessor If the number of address bits in a memory is reduced by 2 and the addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory) Remains unchanged Doubles Halves Increases by 2^(address bits)/addressability Remains unchanged Doubles Halves Increases by 2^(address bits)/addressability ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A mask programmed ROM is erasable electrically erasable and programmable programmed at the time of fabrication programmed by the user erasable electrically erasable and programmable programmed at the time of fabrication programmed by the user ANSWER DOWNLOAD EXAMIANS APP
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