Microprocessor We say that a set of gates is logically complete if we can build any circuit without using any other kind of gates. Which of the following sets are logically complete Set of {AND,OR,NOT} Set of {AND,OR} Set of {EXOR, NOT} None of these Set of {AND,OR,NOT} Set of {AND,OR} Set of {EXOR, NOT} None of these ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The output data lines of microprocessor and memories are usually tristated because More than one device can transmit information over the data bus by enabling only one device at a time The data line can be multiplexed for both input and output More than one device can transmit over the data bus at the same time It increases the speed of data transfer over the data bus More than one device can transmit information over the data bus by enabling only one device at a time The data line can be multiplexed for both input and output More than one device can transmit over the data bus at the same time It increases the speed of data transfer over the data bus ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 name/names of the 16 bit registers is/are both A and B. none of these. stack pointer. program counter. both A and B. none of these. stack pointer. program counter. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor When .9432 E – 4 is subtracted from .5452 E – 3 in normalized floating point mode Both Ihe numbers are changed and their exponents are, made equal to -5 .9432 E – 4 is changed to .09432 E – 3 and .5452 E – 3 is not changed .5452 E – 3 is changed to 5.452 E – 4 but .9432 E – 4 is not changed None of the numbers is changed Both Ihe numbers are changed and their exponents are, made equal to -5 .9432 E – 4 is changed to .09432 E – 3 and .5452 E – 3 is not changed .5452 E – 3 is changed to 5.452 E – 4 but .9432 E – 4 is not changed None of the numbers is changed ANSWER DOWNLOAD EXAMIANS APP
Microprocessor After RESET 8255 will be in mode 2 mode 0; all ports are input mode 0; all ports are output unchanged condition mode 2 mode 0; all ports are input mode 0; all ports are output unchanged condition ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following interrupt is both level and edge sensitive? RST 5.5 TRAP RST 7.5 INTR RST 5.5 TRAP RST 7.5 INTR ANSWER DOWNLOAD EXAMIANS APP
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