Microprocessor Pick up the programmable interrupt controller from the following 8279 8257 8275 8259 8279 8257 8275 8259 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor An I/O processor controls the flow of information between Two I/O devices Cache memory and I/O devices Main memory and I/O devices Cache and main memory Two I/O devices Cache memory and I/O devices Main memory and I/O devices Cache and main memory ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The output data lines of microprocessor and memories are usually tristated because More than one device can transmit information over the data bus by enabling only one device at a time More than one device can transmit over the data bus at the same time It increases the speed of data transfer over the data bus The data line can be multiplexed for both input and output More than one device can transmit information over the data bus by enabling only one device at a time More than one device can transmit over the data bus at the same time It increases the speed of data transfer over the data bus The data line can be multiplexed for both input and output ANSWER DOWNLOAD EXAMIANS APP
Microprocessor RST 3 instruction will cause the processor to branch to the location 0028H 0000H 0018H 0024H 0028H 0000H 0018H 0024H ANSWER DOWNLOAD EXAMIANS APP
Microprocessor XCHG instruction exchanges the content of H-L with ______ register pair. B-C D-E Stack Pointer PSW B-C D-E Stack Pointer PSW ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which one of the following interrupt/interrupts is/are only level triggering? RST 5.5 TRAP both ‘a’ and ‘b’ RST 6.5 RST 5.5 TRAP both ‘a’ and ‘b’ RST 6.5 ANSWER DOWNLOAD EXAMIANS APP
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