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Microprocessor

Microprocessor
Pick out the matching pair

 S0;S1;wait status
 READY; RIM
 SID; SIM
 HOLD; DMA

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Microprocessor
Which of the following interrupt is both level and edge sensitive?

 RST 7.5
 INTR
 TRAP
 RST 5.5

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Microprocessor
Let the content of accumulator and register B be 0000 0100 and 0100 0000 respectively before execution of instruction SUB B. The content of accumulator after the execution of this instruction will be

 01000000
 010001000
 11000100
 00000100

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Microprocessor
Which of the data transfer is not possible in microprocessor

 accumulator to memory
 I/O device to accumulator
 memory to memory
 memory to accumulator

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Microprocessor
Which general register or general register pair is incremented/decremented by 2 during PUSH and POP instructions?

 Program Counter.
 H-L.
 Stack Pointer.
 D-E.

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Microprocessor
During which T-state, contents of OP code from memory are loaded into IR (Instruction Register)?

 T2 OP code fetch
 T1 OP code fetch
 T4 OP code fetch
 T3 OP code fetch

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