Microprocessor Pick out the matching pair SID; SIM HOLD; DMA S0;S1;wait status READY; RIM SID; SIM HOLD; DMA S0;S1;wait status READY; RIM ANSWER DOWNLOAD EXAMIANS APP
Microprocessor At the beginning of a fetch cycle, the contents of the program counter are transferred to memory address register . incremented by one. transferred to address bus. transferred to memory data register. transferred to memory address register . incremented by one. transferred to address bus. transferred to memory data register. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. Both ‘b’ and ‘c’ None of these Bus Interface Unit (BIU) Execution Unit (EU) Both ‘b’ and ‘c’ None of these Bus Interface Unit (BIU) Execution Unit (EU) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In a vector interrupt the interrupting source supplies the branch information to the processor through an interrupt vector. the branch address is obtained from a register in the processor. the branch address is assigned to a fixed location in memory. none. the interrupting source supplies the branch information to the processor through an interrupt vector. the branch address is obtained from a register in the processor. the branch address is assigned to a fixed location in memory. none. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor ________is the only non-vectored interrupt in 8085 microprocessor. RST 5.5 RST 7 TRAP INTR RST 5.5 RST 7 TRAP INTR ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In order to save accumulator value on the stack, which of the following instruction may be used POP PSW PUSH PSW PUSH SP PUSH A POP PSW PUSH PSW PUSH SP PUSH A ANSWER DOWNLOAD EXAMIANS APP
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