Microprocessor If the number of address bits in a memory is reduced by 2 and the addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory) Halves Doubles Increases by 2^(address bits)/addressability Remains unchanged Halves Doubles Increases by 2^(address bits)/addressability Remains unchanged ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The processor status word of 8085 microprocessor has five flags namely: S, Z, AC, P, CY S, OV, AC, P, CY S, Z, OV, P, CY S, Z, AC, P, OV S, Z, AC, P, CY S, OV, AC, P, CY S, Z, OV, P, CY S, Z, AC, P, OV ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Both the ALU and control section of CPU employ which special purpose storage location? Buffers Decoders Accumulators Registers Buffers Decoders Accumulators Registers ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Monostablemultivibrators (IC74121) are used in a microprocessor based system for frequency measurement. Reason(R): Microprocessor counts the number of interrupt signals/second or within a specified interval through ISR. A is true but R is false. Both A & R are true but R is not the correct explanation of A. A is false but R is true. Both A & R are true and R is the correct explanation of A. A is true but R is false. Both A & R are true but R is not the correct explanation of A. A is false but R is true. Both A & R are true and R is the correct explanation of A. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In order to save accumulator value on the stack, which of the following instruction may be used PUSH PSW PUSH SP PUSH A POP PSW PUSH PSW PUSH SP PUSH A POP PSW ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following interrupt is both level and edge sensitive? INTR TRAP RST 5.5 RST 7.5 INTR TRAP RST 5.5 RST 7.5 ANSWER DOWNLOAD EXAMIANS APP
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