Microprocessor If the number of address bits in a memory is reduced by 2 and the addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory) Halves Increases by 2^(address bits)/addressability Remains unchanged Doubles Halves Increases by 2^(address bits)/addressability Remains unchanged Doubles ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In an 8085 microprocessor based system, the contents of SP are 1000H, PUSH B instruction will transfer the contents of registers B & C respectively for memory locations 0FFE H and 0FFF H 1000 H and 0FFF H 1000 H and 1001 H 0FFF H and 0FFE H 0FFE H and 0FFF H 1000 H and 0FFF H 1000 H and 1001 H 0FFF H and 0FFE H ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In a microprocessor based system the stack is always in ROM EPROM microprocessor RAM ROM EPROM microprocessor RAM ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The operating modes of 8255 A are called Mode 0 and mode 1 Mode 0, mode 2 and mode 3 Mode 0 and mode 2 Mode 0, mode 1 and mode 2 Mode 0 and mode 1 Mode 0, mode 2 and mode 3 Mode 0 and mode 2 Mode 0, mode 1 and mode 2 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor HLDA signal in 8085 performs the following operation: Hold the data in the accumulator until the microprocessor is turned OFF. Indicates that the CPU has not received the HOLD request. Indicates that the CPU has received the HOLD request and that it will relinquish the bus in the next clock cycle. Indicates that another master is requesting the use of the address and data buses. Hold the data in the accumulator until the microprocessor is turned OFF. Indicates that the CPU has not received the HOLD request. Indicates that the CPU has received the HOLD request and that it will relinquish the bus in the next clock cycle. Indicates that another master is requesting the use of the address and data buses. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Ready signal of microprocessor is used to detect whether a peripheral is ready for the data transfer or not. Reason(R): In the microprocessor during data transfer operations, the wait states are added by forcing the ready signal low. Both A & R are true and R is the correct explanation of A. A is false but R is true. Both A & R are true but R is not the correct explanation of A . A is true but R is false. Both A & R are true and R is the correct explanation of A. A is false but R is true. Both A & R are true but R is not the correct explanation of A . A is true but R is false. ANSWER DOWNLOAD EXAMIANS APP
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