Microprocessor ‘Burst refresh’ in DRAM is also called Hidden refresh Concentrated refresh Distributed refresh None of these Hidden refresh Concentrated refresh Distributed refresh None of these ANSWER DOWNLOAD EXAMIANS APP
Microprocessor SUB A instruction in 8085 sets zero and carry flags reset carry and sign flags sets zero and sign flags reset zero and parity flags sets zero and carry flags reset carry and sign flags sets zero and sign flags reset zero and parity flags ANSWER DOWNLOAD EXAMIANS APP
Microprocessor When the write enable input is not asserted, the gated D latch _________ its output. Complements Clears Can not change Sets Complements Clears Can not change Sets ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following conditions is not allowed in an RS latch? R is asserted, S is asserted R is negated, S is asserted R is negated, S is negated R is asserted, S is negated R is asserted, S is asserted R is negated, S is asserted R is negated, S is negated R is asserted, S is negated ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assuming LSB is at position 0 and MSB at position 7, which bit positions are not used (Undefined) in flag register of an 8085 microprocessor? 1, 3, 5 2, 3, 5 1, 2, 5 1, 3, 4 1, 3, 5 2, 3, 5 1, 2, 5 1, 3, 4 ANSWER DOWNLOAD EXAMIANS APP
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