Microprocessor Identify the non-maskable interrupt from the following RST 5.5 RST 6.5 RST 7.5 RST 4.5 RST 5.5 RST 6.5 RST 7.5 RST 4.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assuming LSB is at position 0 and MSB at position 7, which bit positions are not used (Undefined) in flag register of an 8085 microprocessor? 2, 3, 5 1, 3, 4 1, 3, 5 1, 2, 5 2, 3, 5 1, 3, 4 1, 3, 5 1, 2, 5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following is not true during the execution of an interrupt service routine, which does not contain any EI instructions the microprocessor cannot be interrupted by any mask able interrupt all interrupts except non-maskable interrupt are disabled the microprocessor cannot be interrupted by any interrupt the microprocessor can be interrupted by a non-mask able interrupt the microprocessor cannot be interrupted by any mask able interrupt all interrupts except non-maskable interrupt are disabled the microprocessor cannot be interrupted by any interrupt the microprocessor can be interrupted by a non-mask able interrupt ANSWER DOWNLOAD EXAMIANS APP
Microprocessor SUB A instruction in 8085 sets zero and sign flags reset carry and sign flags sets zero and carry flags reset zero and parity flags sets zero and sign flags reset carry and sign flags sets zero and carry flags reset zero and parity flags ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Let the content of register C be 00000000 before the instruction DCR C is executed. The content of register C after the after the execution of this instruction will be 00000001 00000000 None 11111111 00000001 00000000 None 11111111 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. Execution Unit (EU) None of these Both ‘b’ and ‘c’ Bus Interface Unit (BIU) Execution Unit (EU) None of these Both ‘b’ and ‘c’ Bus Interface Unit (BIU) ANSWER DOWNLOAD EXAMIANS APP
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