Microprocessor Which of the following instruction is not possible in 8085? POP B POP PSW POP D POP 30 H POP B POP PSW POP D POP 30 H ANSWER DOWNLOAD EXAMIANS APP
Microprocessor HLDA signal in 8085 performs the following operation: Indicates that the CPU has received the HOLD request and that it will relinquish the bus in the next clock cycle. Indicates that the CPU has not received the HOLD request. Indicates that another master is requesting the use of the address and data buses. Hold the data in the accumulator until the microprocessor is turned OFF. Indicates that the CPU has received the HOLD request and that it will relinquish the bus in the next clock cycle. Indicates that the CPU has not received the HOLD request. Indicates that another master is requesting the use of the address and data buses. Hold the data in the accumulator until the microprocessor is turned OFF. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Identify the non-maskable interrupt from the following RST 6.5 RST 5.5 RST 4.5 RST 7.5 RST 6.5 RST 5.5 RST 4.5 RST 7.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The length of bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an indeterminate number of wait state clock cycles denoted by Tw. The wait states are always inserted between T2 & T3 T3 & T4 T1 & T2 T4 & T1 T2 & T3 T3 & T4 T1 & T2 T4 & T1 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The content of the A15-A8 (higher order address lines) while executing “IN 8-bit port address” instruction are same as the content of A7-A0 all bits set (i.e. FFH) irrelevant all bits reset (i.e. 00H) same as the content of A7-A0 all bits set (i.e. FFH) irrelevant all bits reset (i.e. 00H) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor ‘Burst refresh’ in DRAM is also called Hidden refresh Distributed refresh Concentrated refresh None of these Hidden refresh Distributed refresh Concentrated refresh None of these ANSWER DOWNLOAD EXAMIANS APP
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