In the given diagram all are NOR Gate . The final output is shown in the figure.
At stage 1 the output will be \overline A \& \overline B
At stage 2 the output will be \overline {\overline A + \overline B } = A.B
And the final output will be \overline {A.B}
Hence for input A & B the output is \overline {AB} in case of Nand gate.