Digital Electronics The output of a NAND gate is low only when all the inputs are low only when all the inputs are high only when at least one input is low only when at least one input is high only when all the inputs are low only when all the inputs are high only when at least one input is low only when at least one input is high ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics Which of the following gate is a two-level logic gate OR gate EXCLUSIVE OR gate NOT gate NAND gate OR gate EXCLUSIVE OR gate NOT gate NAND gate ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics A 15-bit Hamming code requires 15 parity bits 4 parity bits none of these. 5 parity bits 15 parity bits 4 parity bits none of these. 5 parity bits ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics Odd parity of a bit stream can be tested using ________ gate. OR AND XOR NOR OR AND XOR NOR ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics Which one of the following is correct sequence of the numbers represented in the series(2)3, (10)4, (11)5, (14)6, (22)7,……………. 2, 4, 6, 10, 12, … 2, 3, 4, 5, 6, …. 2, 4, 6, 10, 16…….. 2, 4, 6, 8, 10, ….. 2, 4, 6, 10, 12, … 2, 3, 4, 5, 6, …. 2, 4, 6, 10, 16…….. 2, 4, 6, 8, 10, ….. ANSWER DOWNLOAD EXAMIANS APP
Digital Electronics Which type of CPLD packaging can provide maximum number of pins on the package due to small size of the pins? BGA PGA PLCC QFP BGA PGA PLCC QFP ANSWER DOWNLOAD EXAMIANS APP
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