Microprocessor The content of the A15-A8 (higher order address lines) while executing “IN 8-bit port address” instruction are all bits reset (i.e. 00H) irrelevant same as the content of A7-A0 all bits set (i.e. FFH) all bits reset (i.e. 00H) irrelevant same as the content of A7-A0 all bits set (i.e. FFH) ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The number of output pins in 8085 microprocessors are 40. 19. 21. 27. 40. 19. 21. 27. ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8085 microprocessor which one of the following statement is wrong there is a pin available for serial input serial I/O is possible through SIM and RIM instruction there is a pin available for serial output serial I/O is not possible there is a pin available for serial input serial I/O is possible through SIM and RIM instruction there is a pin available for serial output serial I/O is not possible ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following pair of gates can form a latch? A cross coupled NAND/OR A pair of cross copled AND A pair of cross coupled OR A pair of cross coupled NAND A cross coupled NAND/OR A pair of cross copled AND A pair of cross coupled OR A pair of cross coupled NAND ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Total numbers of output pins in 8085 microprocessor are 40 13 30 27 40 13 30 27 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor In 8086, _______ uses a mechanism known as an instruction stream queue to implement a pipeline architecture. None of these Execution Unit (EU) Both ‘b’ and ‘c’ Bus Interface Unit (BIU) None of these Execution Unit (EU) Both ‘b’ and ‘c’ Bus Interface Unit (BIU) ANSWER DOWNLOAD EXAMIANS APP
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