Microprocessor
The content of the A15-A8 (higher order address lines) while executing “IN 8-bit port address” instruction are

 all bits reset (i.e. 00H)
 irrelevant
 all bits set (i.e. FFH)
 same as the content of A7-A0

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Microprocessor
Cycle stealing mode of DMA operation involves

 Data transfer takes place between the I/O device and memory during every alternate clock cycle
 DMA controller taking over the address, data and control buses while a block of data is transferred between memory and I/O device
 While the microprocessor is executing a program an interface circuit takes over control of address, data, control buses when not in use by microprocessor
 The DMA control waiting for the microprocessor to finish execution of the program and then takes over the buses

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Microprocessor
HLDA signal in 8085 performs the following operation:

 Indicates that another master is requesting the use of the address and data buses.
 Hold the data in the accumulator until the microprocessor is turned OFF.
 Indicates that the CPU has received the HOLD request and that it will relinquish the bus in the next clock cycle.
 Indicates that the CPU has not received the HOLD request.

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