Microprocessor SUB A instruction in 8085 reset zero and parity flags sets zero and carry flags reset carry and sign flags sets zero and sign flags reset zero and parity flags sets zero and carry flags reset carry and sign flags sets zero and sign flags ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The length of bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an indeterminate number of wait state clock cycles denoted by Tw. The wait states are always inserted between T2 & T3 T3 & T4 T1 & T2 T4 & T1 T2 & T3 T3 & T4 T1 & T2 T4 & T1 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The relation among IC (Instruction Cycle), FC (Fetch cycle) and EC (Execute Cycle) is IC = FC - EC IC = FC + EC IC = FC + 2EC EC = IC + FC IC = FC - EC IC = FC + EC IC = FC + 2EC EC = IC + FC ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The operations executed by two or more control units are referred as Micro-operations Bi control-operations Multi-operations Macro-operations Micro-operations Bi control-operations Multi-operations Macro-operations ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Assertion(A): Address bus is unidirectional. Reason(R): Data bus is bidirectional A is false but R is true Both A & R are true but R is not the correct explanation of A Both A & R are true and R is the correct explanation of A A is true but R is false A is false but R is true Both A & R are true but R is not the correct explanation of A Both A & R are true and R is the correct explanation of A A is true but R is false ANSWER DOWNLOAD EXAMIANS APP
Microprocessor A sequence of two registers that multiplies the content of DE register pair by two and stores the result in HL register pair (in 8085 assembly language) is XTHL & DAD H PCHL & DAD D XCHG & DAD B XCHG & DAD H XTHL & DAD H PCHL & DAD D XCHG & DAD B XCHG & DAD H ANSWER DOWNLOAD EXAMIANS APP
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