Microprocessor RST 3 instruction will cause the processor to branch to the location 0000H 0028H 0018H 0024H 0000H 0028H 0018H 0024H ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following instruction will never affect the zero flag? DCR R DCX Rp XRA R ORA R DCR R DCX Rp XRA R ORA R ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which of the following conditions is not allowed in an RS latch? R is negated, S is asserted R is negated, S is negated R is asserted, S is negated R is asserted, S is asserted R is negated, S is asserted R is negated, S is negated R is asserted, S is negated R is asserted, S is asserted ANSWER DOWNLOAD EXAMIANS APP
Microprocessor The data lines of 8085 microprocessor are multiplexed with None of these status lines higher order address lines lower order address lines None of these status lines higher order address lines lower order address lines ANSWER DOWNLOAD EXAMIANS APP
Microprocessor Which one of the following interrupt/interrupts is/are only level triggering? RST 6.5 both ‘a’ and ‘b’ TRAP RST 5.5 RST 6.5 both ‘a’ and ‘b’ TRAP RST 5.5 ANSWER DOWNLOAD EXAMIANS APP
Microprocessor While STC instruction executes, only carry and zero flags will be affected. no flags will be affected. all flags will be affected. only carry flag will be affected. only carry and zero flags will be affected. no flags will be affected. all flags will be affected. only carry flag will be affected. ANSWER DOWNLOAD EXAMIANS APP
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